Patents by Inventor Kai Chang

Kai Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11521929
    Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: December 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin Liang, Chun-I Tsai, Chih-Wei Chang, Chun-Hsien Huang, Hung-Yi Huang, Keng-Chu Lin, Ken-Yu Chang, Sung-Li Wang, Chia-Hung Chu, Hsu-Kai Chang
  • Publication number: 20220384601
    Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsu-Kai CHANG, Jhih-Rong HUANG, Yen-Tien TUNG, Chia-Hung CHU, Shuen-Shin LIANG, Tzer-Min SHEN, Pinyen LIN, Sung-Li WANG
  • Publication number: 20220380392
    Abstract: The present disclosure is directed to organotin cluster compounds having formula (I) and their use as photoresists in extreme ultraviolet lithography processes.
    Type: Application
    Filed: July 21, 2022
    Publication date: December 1, 2022
    Inventors: Hsu-Kai CHANG, Chi-Ming YANG, Jui-Hsiung LIU, Jui-Hung FU, Hsin-Yi WU
  • Patent number: 11514914
    Abstract: Systems and methods for an intelligent virtual assistant for meetings are disclosed. In one embodiment, a system for an intelligent virtual assistant for meeting may include a server comprising at least one computer processor executing a virtual assistant computer program; a communication server in communication with the server; and a plurality of communication devices in communication with the server and the communication server, wherein the communication server facilitates an electronic meeting with a plurality of attendees via the plurality of communication devices. The virtual assistant may receive at least an audio feed and a video feed of the electronic meeting in real-time, may transcribe the audio feed using a speech-recognition algorithm, may provide the transcription to at least one of the plurality of attendees, may receive an edited transcription, and may update the speech recognition algorithm based on the edited transcription.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: November 29, 2022
    Assignee: JPMORGAN CHASE BANK, N.A.
    Inventors: Daniel D McQuiston, Aarti Narayanan, Dave Burrells, Simon Burke, Jan S Dabrowski, Rhys Dawes, Charlotte Knight, Libby Kent, Sandeep Koul, Uday Pant, Tony M Nazarowski, Aditi Vaidya, Ayush Kumar Bilala, Charanjith Allaparambil Chandran, Prayag Godha, Nikhil Kotikanikadanam Madhusudhan, Chitra Pillai Sundaribai, Aditya Anil Upadhyay, Eric Han Kai Chang, Stefan Cristian Bardasu, Erin Michelle Perry, Saifuddin Merchant, James P White, III
  • Publication number: 20220375868
    Abstract: A semiconductor device includes a gate electrode, a source/drain structure, a lower contact contacting either of the gate electrode or the source/drain structure, and an upper contact disposed in an opening formed in an interlayer dielectric (ILD) layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without an interposing conductive barrier layer, and the upper contact includes ruthenium.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 24, 2022
    Inventors: Cheng-Wei CHANG, Chia-Hung CHU, Kao-Feng LIN, Hsu-Kai CHANG, Shuen-Shin LIANG, Sung-Li WANG, Yi-Ying LIU, Po-Nan YEH, Yu Shih WANG, U-Ting CHIU, Chun-Neng LIN, Ming-Hsi YEH
  • Publication number: 20220367660
    Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.
    Type: Application
    Filed: May 14, 2021
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin Liang, Chih-Chien Chi, Chien-Shun Liao, Keng-Chu Lin, Kai-Ting Huang, Sung-Li Wang, Yi-Ying Liu, Chia-Hung Chu, Hsu-Kai Chang, Cheng-Wei Chang
  • Publication number: 20220367662
    Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.
    Inventors: Shuen-Shin Liang, Chun-I Tsai, Chih-Wei Chang, Chun-Hsien Huang, Hung-Yi Huang, Keng-Chu Lin, Ken-Yu Chang, Sung-Li Wang, Chia-Hung Chu, Hsu-Kai Chang
  • Patent number: 11494870
    Abstract: An exemplary video processing method includes: receiving an omnidirectional content corresponding to a sphere; obtaining a plurality of projection faces from the omnidirectional content of the sphere according to a pyramid projection; creating at least one padding region; and generating a projection-based frame by packing the projection faces and the at least one padding region in a pyramid projection layout. The projection faces packed in the pyramid projection layout include a first projection face. The at least one padding region packed in the pyramid projection layout includes a first padding region. The first padding region connects with at least the first projection face, and forms at least a portion of one boundary of the pyramid projection layout.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: November 8, 2022
    Assignee: MEDIATEK INC.
    Inventors: Jian-Liang Lin, Peng Wang, Ya-Hsuan Lee, Hung-Chih Lin, Shen-Kai Chang
  • Patent number: 11489057
    Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: November 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsu-Kai Chang, Jhih-Rong Huang, Yen-Tien Tung, Chia-Hung Chu, Shuen-Shin Liang, Tzer-Min Shen, Pinyen Lin, Sung-Li Wang
  • Patent number: 11476772
    Abstract: A voltage converter circuit, comprising: a bridge rectifier; a first transistor, having a first end, a second end and a third end; a second transistor, having a first end and a second end; wherein the first end of the first transistor and the first end of second transistor are electrically connected to bridge rectifier, and the second end of the first transistor is electrically connected to the first end of the second transistor; and a Zener diode, connected between the third end of the first transistor and the second end of the second transistor.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: October 18, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Sheng-Bo Wang, Chiao Fu, Chang-Hsieh Wu, Jai-Tai Kuo, Chao-Kai Chang, Yao-Zhong Liu, Yi-Ru Shen, Chen-Yu Wang
  • Publication number: 20220302729
    Abstract: In some examples a computing device, comprising a battery, a processing resource and a memory resource storing non-transitory machine-readable instructions can cause the processing resource to determine a battery charge capacity of the battery, in response to the battery charge capacity being less than a threshold capacity, cause the battery to charge, and in response to the battery charge capacity being greater than the threshold capacity, compare the battery charge capacity of the computing device with a different battery charge capacity associated with a different computing device, and based on the comparison, cause a charge determination event to occur.
    Type: Application
    Filed: November 8, 2019
    Publication date: September 22, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Wei-Chih Huang, Chih-Kai Chang, Po Chin Chung, Chao-Shen Chen
  • Publication number: 20220301822
    Abstract: An embodiment is an apparatus, such as a plasma chamber. The apparatus includes chamber walls and a chamber window defining an enclosed space. A chamber window is disposed between a plasma antenna and a substrate support. A gas delivery source is mechanically coupled to the chamber window. The gas delivery source comprises a gas injector having a passageway, a window at a first end of the passageway, and a nozzle at a second end of the passageway. The nozzle of the gas delivery source is disposed in the enclosed space. A fastening device is mechanically coupled to the gas delivery source. The fastening device is adjustable to adjust a sealing force against the gas injector.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Inventors: Yung-Shun HSU, Ching-Yu CHANG, Chiao-Kai CHANG, Wai Hong CHEAH, Chien-Fang LIN
  • Publication number: 20220299891
    Abstract: An extreme ultraviolet (EUV) source includes a module vessel and a scrubber system. The scrubber system may include a plurality of gutters in the module vessel. The plurality of gutters may include a first gutter and a second gutter. The second gutter may be lower than the first gutter in the module vessel. A unit volume of the second gutter is larger than a unit volume of the first gutter.
    Type: Application
    Filed: August 27, 2021
    Publication date: September 22, 2022
    Inventors: Chun-Kai CHANG, Yu Sheng CHIANG, Yu De LIOU, Chi YANG, Ching-Juinn HUANG, Po-Chung CHENG
  • Patent number: 11441329
    Abstract: A handle locking structure includes a handle having a pivot portion pivotally connected to a sliding box, a buckle portion for hooking on a cabinet and a handle shaft, and a positioning structure including a base connected to the handle shaft, a positioning device mounted in the base and an elastic member placed on the positioning device. When the handle is hooked on the cabinet, a peripheral limiter of a head member of the positioning device is disengaged from a position-limiting notch of the base to reset the elastic member, so that the positioning device is automatically locked to the sliding box, avoiding vibration of the handle and improving the locking stability of the handle.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: September 13, 2022
    Assignee: HANWIT PRECISION INDUSTRIES LTD.
    Inventors: Ying-Chih Tseng, Ching-Kai Chang
  • Patent number: 11443994
    Abstract: The present application provides an electronic package having an optoelectronic component and a laser component disposed on a packaging unit, with the optoelectronic component and the laser component being separated from each other. Since the laser component and the optoelectronic component are separated from each other, the electronic package has a reduced fabrication difficulty and a high yield rate. A method for fabricating the electronic package and an electronic packaging module having the electronic package are also provided.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: September 13, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Jin-Wei You, Cheng-Kai Chang
  • Publication number: 20220283506
    Abstract: A control system includes a plurality of pressure sensors, each to detect a pressure in a respective dynamic gas lock (DGL) nozzle control region of a plurality of DGL nozzle control regions. Each DGL nozzle control region includes one or more DGL nozzles. The control system includes a plurality of mass flow controllers (MFCs). Each MFC of the plurality of MFCs is to control a flow velocity in a respective DGL nozzle control region of the plurality of DGL nozzle control regions. The control system includes a controller to selectively cause one or more MFCs of the plurality of MFCs to adjust flow velocities in one or more DGL nozzle control regions of the plurality of DGL nozzle control regions based on pressures detected by the plurality of pressure sensors in DGL nozzle control regions of the plurality of DGL nozzle control regions.
    Type: Application
    Filed: August 27, 2021
    Publication date: September 8, 2022
    Inventors: Chun-Kai CHANG, Yu Sheng CHIANG, Yu De LIOU, Chi YANG, Ching-Juinn HUANG, Po-Chung CHENG
  • Patent number: 11436586
    Abstract: Systems and methods for account agnostic transaction routing are disclosed. According to one embodiment, in an information processing device comprising at least one computer processor, a method for account agnostic transaction routing may include: (1) receiving an identifier for a first financial instrument for a transaction being conducted at a point of transaction; (2) retrieving a plurality of financial instruments associated with the identifier, the plurality of financial instruments comprising the first financial instrument; (3) retrieving at least one transaction routing rule associated with the plurality of financial instruments, the transaction routing rule specifying a condition for using one of the plurality of financial instruments; (4) identifying one of the plurality of financial instruments for conducting the transaction based on the transaction and the transaction routing rule; and (5) settling the transaction with the identified financial instrument.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 6, 2022
    Assignee: JPMORGAN CHASE BANK, N.A.
    Inventors: James P. White, III, Eric Han Kai Chang, Howard Spector, William F. Mann, III
  • Publication number: 20220276469
    Abstract: A lens assembly includes a first lens, a second lens, a third lens, a fourth lens, and a fifth lens. The first lens is a meniscus lens with negative refractive power. The second lens is with positive refractive power and includes a convex surface facing an image side. The third lens is a meniscus lens with positive refractive power. The fourth lens is with positive refractive power. The fifth lens is with refractive power and includes a convex surface facing an object side. The first lens, the second lens, the third lens, the fourth lens, and the fifth lens are arranged in order from an object side to the image side along an optical axis.
    Type: Application
    Filed: February 7, 2022
    Publication date: September 1, 2022
    Inventors: An-Kai Chang, Wen-Chieh Chen
  • Patent number: 11424185
    Abstract: A semiconductor device includes a gate electrode, a source/drain structure, a lower contact contacting either of the gate electrode or the source/drain structure, and an upper contact disposed in an opening formed in an interlayer dielectric (ILD) layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without an interposing conductive barrier layer, and the upper contact includes ruthenium.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Wei Chang, Chia-Hung Chu, Kao-Feng Lin, Hsu-Kai Chang, Shuen-Shin Liang, Sung-Li Wang, Yi-Ying Liu, Po-Nan Yeh, Yu Shih Wang, U-Ting Chiu, Chun-Neng Lin, Ming-Hsi Yeh
  • Publication number: 20220245861
    Abstract: An image processing method includes: performing content analysis upon an input frame to generate at least one content analysis result of the input frame; determining, by a processing circuit, an anti-blue light strength level for the input frame according to content analysis result(s) of the input frame; and in response to the anti-blue light strength level determined for the input frame, performing color correction upon the input frame to generate an output frame.
    Type: Application
    Filed: August 3, 2021
    Publication date: August 4, 2022
    Applicant: MEDIATEK INC.
    Inventors: Chih-Kai Chang, Shuo-Li Shih, Tsu-Ming Liu, Yung-Chang Chang