Abstract: A vertically integrated micro-bolometer includes an integrated circuit chip, an infrared sensing film, and a metal bonding layer. The integrated circuit chip includes a silicon substrate, a circuit element, and a dielectric layer disposed on the silicon substrate. The infrared sensing film includes a top absorbing layer, a sensing layer, and a bottom absorbing layer. The sensing layer is disposed between the top absorbing layer and the bottom absorbing layer. Materials of the top absorbing layer, the sensing layer, and the bottom absorbing layer are materials compatible with a semiconductor manufacturing process. The metal bonding layer connects the dielectric layer on the silicon substrate in the integrated circuit chip and the bottom absorbing layer of the infrared sensing film to form a vertically integrated micro-bolometer. In one embodiment, the infrared sensing film is divided into a central sensing film, a surrounding sensing film, and a plurality of connecting portions by a plurality of slots.

Abstract: A probe station includes a frame, a platform, a testing equipment, a probe holder and at least one probe. The frame defines an accommodation space. The platform is connected with the frame. The platform has an opening. The opening is communicated with the accommodation space. The testing equipment is at least partially disposed in the accommodation space and is at least partially exposed through the opening. The probe holder is disposed on the platform. The probe is held by the probe holder. The probe holder is configured to control the probe to contact with a device under test disposed on the testing equipment through the opening.

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first fin-shaped structure between the first epitaxial layer and the substrate, and a first contact plug between the first epitaxial layer and the second epitaxial layer. Preferably, the first gate structure includes a gate dielectric layer, top surfaces of the gate dielectric layer and the first fin-shaped structure are coplanar, and a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug.

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

Abstract: A probe station includes a frame, a platform, a testing equipment, a probe holder and at least one probe. The frame defines an accommodation space. The platform is connected with the frame. The platform has an opening. The opening is communicated with the accommodation space. The testing equipment is at least partially disposed in the accommodation space and is at least partially exposed through the opening. The probe holder is disposed on the platform. The probe is held by the probe holder. The probe holder is configured to control the probe to contact with a device under test disposed on the testing equipment through the opening.

Abstract: A vertically integrated micro-bolometer includes an integrated circuit chip, an infrared sensing film, and a metal bonding layer. The integrated circuit chip includes a silicon substrate, a circuit element, and a dielectric layer disposed on the silicon substrate. The infrared sensing film includes a top absorbing layer, a sensing layer, and a bottom absorbing layer. The sensing layer is disposed between the top absorbing layer and the bottom absorbing layer. Materials of the top absorbing layer, the sensing layer, and the bottom absorbing layer are materials compatible with a semiconductor manufacturing process. The metal bonding layer connects the dielectric layer on the silicon substrate in the integrated circuit chip and the bottom absorbing layer of the infrared sensing film to form a vertically integrated micro-bolometer. In one embodiment, the infrared sensing film is divided into a central sensing film, a surrounding sensing film, and a plurality of connecting portions by a plurality of slots.

Abstract: A probe station includes a frame, a platform, a testing equipment, a probe holder and at least one probe. The frame defines an accommodation space. The platform is connected with the frame. The platform has an opening. The opening is communicated with the accommodation space. The testing equipment is at least partially disposed in the accommodation space and is at least partially exposed through the opening. The probe holder is disposed on the platform. The probe is held by the probe holder. The probe holder is configured to control the probe to contact with a device under test disposed on the testing equipment through the opening.

Abstract: A probe station includes a frame, a platform, a testing equipment, a probe holder and at least one probe. The frame defines an accommodation space. The platform is connected with the frame. The platform has an opening. The opening is communicated with the accommodation space. The testing equipment is at least partially disposed in the accommodation space and is at least partially exposed through the opening. The probe holder is disposed on the platform. The probe is held by the probe holder. The probe holder is configured to control the probe to contact with a device under test disposed on the testing equipment through the opening.

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

Abstract: The present application provides a testing system. The testing system includes a chip socket and a probe. The chip socket includes a pedestal and a fastener. The pedestal is configured to accommodate a chip to be tested. The fastener includes a top body and a base body. The top body includes a probing window surrounded by a plurality of side walls, wherein the probing window has a first end at an outer surface of the top body and a second end at an inner surface of the top body, a first angle between a first side wall of the plurality of side walls and the outer surface is less than 90 degrees, and a first opening area at the first end of the probing window is larger than a second opening area at the second end of the probing window.

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

Abstract: The present application discloses a chip socket for testing a semiconductor chip. The chip socket includes a pedestal and a fastener. The pedestal accommodates a chip to be tested. The fastener includes a top body and a base body. The top body includes a probing window, wherein a first opening area of the probing window at an outer surface of the top body is larger than a second opening area of the probing window at an inner surface of the top body. The base body is attached to the pedestal and locked to the top body when the top body covers the base body and clamps the chip. When the top body covers the base body, the probing window reveals a surface of the chip, allowing a probe to contact the surface of the chip through the probing window.

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

Abstract: A microneedle electroporation device is provided, including a housing, a positioning member, an intermediate plate, a first microneedle assembly, a second microneedle assembly, a socket, a first wire, and a second wire. The positioning member is connected to the housing and the intermediate plate. The intermediate plate includes a plurality of first holes and a plurality of second holes. The first microneedle assembly includes a plurality of first microneedles and a first metal connecting portion connected to the first microneedles. The first microneedles pass through the first holes. The second microneedle assembly includes a plurality of second microneedles and a second metal connecting portion connected to the second microneedles. The second microneedles pass through the second holes. The first microneedle assembly and the second microneedle assembly are electrically independent of each other. The first wire connects the socket to the first metal connecting portion.

Abstract: An OS-independent peripheral plug-and-play and driver update method for embedded system and firmware data transmission method for embedded system platform is provided. The method includes: determining whether a peripheral device is connected to the embedded system host; when the peripheral device is connected to the embedded system host, acquire the ID of the peripheral device; connecting to a firmware server; according to the ID, acquiring a driver; packing the driver into a firmware and transmitting to the embedded system host; and performing a firmware update.

Abstract: An optical detecting device includes an image capturing device and a processor. The processor is coupled to a light source and an image capturing device. The processor is configured to adjust a light intensity of the light source for irradiating a correction object in order that a gray value of at least one image block, captured by the image capturing device, of the correction object matches a target correction value, and record a target light intensity while the target light intensity matches the target correction value; control the light source to irradiate light on a testing object with the target light intensity, and control the image capturing device to capture a testing object image of the testing object; and calculate ratios of a target gray value to the gray value of a plurality of pixels of the testing object image to obtain a mapping table.

Abstract: An optical detecting device includes an image capturing device and a processor. The processor is coupled to a light source and an image capturing device. The processor is configured to adjust a light intensity of the light source for irradiating a correction object in order that a gray value of at least one image block, captured by the image capturing device, of the correction object matches a target correction value, and record a target light intensity while the target light intensity matches the target correction value; control the light source to irradiate light on a testing object with the target light intensity, and control the image capturing device to capture a testing object image of the testing object; and calculate ratios of a target gray value to the gray value of a plurality of pixels of the testing object image to obtain a mapping table.

Abstract: A high-frequency connecting device includes a housing, a sandwiched member, an inner heat sink, a rear heat sink, a heat pipe, a upper heat sink and a connector. The inner heat sink is disposed inside the sandwiched member. The top and the bottom of the inner heat sink respectively have a first contact portion and a second contact portion. The upper heat sink has a third contact portion. A fourth contact portion is elastically disposed on the lower cover. The first and the second optical modules are respectively inserted into the upper and the lower spaces. The top and the bottom of the first optical module are in direct contact respectively with the third contact portion and the first contact portion, while the top and the bottom of the second optical module are in direct contact respectively with the second contact portion and the fourth contact portion.

Abstract: A system and method for the federation of content items of a social network based on personalized relevance includes obtaining content items from first and second content item sources. Profile data for a member of the social network is obtained from the electronic data storage. A relevance score of the content item to the profile data of the member is determined for each of the content items. A utility value is determined based on the selection value, the value metric for content items from the first content item source, and the relevance score. A user device associated with the member displays the content items based on their respective utility values.