Patents by Inventor Kai Chat Tan

Kai Chat Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor package with grounding device and related methods
    Patent number: 10699989
    Abstract: Implementations of a semiconductor package may include a first side of a die coupled to a first side of an electrically insulative layer, a second side of the electrically insulative layer coupled to a lead frame, and at least one ground stud physically coupled to the lead frame and to the die, the at least one ground stud extending from the second side of the electrically insulative layer into the electrically insulative layer from the lead frame. The die may be wire bonded to the lead frame.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: June 30, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atapol Prajuckamol, Sw Wang, Kai Chat Tan
  • SEMICONDUCTOR PACKAGE WITH GROUNDING DEVICE AND RELATED METHODS
    Publication number: 20190122963
    Abstract: Implementations of a semiconductor package may include a first side of a die coupled to a first side of an electrically insulative layer, a second side of the electrically insulative layer coupled to a lead frame, and at least one ground stud physically coupled to the lead frame and to the die, the at least one ground stud extending from the second side of the electrically insulative layer into the electrically insulative layer from the lead frame. The die may be wire bonded to the lead frame.
    Type: Application
    Filed: July 10, 2018
    Publication date: April 25, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atapol PRAJUCKAMOL, Sw WANG, Kai Chat TAN
  • Semiconductor package with grounding device and related methods
    Patent number: 10056317
    Abstract: Implementations of a semiconductor package may include a first side of a die coupled to a first side of an electrically insulative layer, a second side of the electrically insulative layer coupled to a lead frame, and at least one ground stud physically coupled to the lead frame and to the die, the at least one ground stud extending from the second side of the electrically insulative layer into the electrically insulative layer from the lead frame. The die may be wire bonded to the lead frame.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: August 21, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atapol Prajuckamol, Sw Wang, Kai Chat Tan
  • METHOD AND SYSTEM FOR EXTENDING DIE SIZE AND PACKAGED SEMICONDUCTOR DEVICES INCORPORATING THE SAME
    Publication number: 20160104662
    Abstract: A packaged semiconductor device includes a die flag and a plurality of lead frame fingers each having a proximate end spaced apart from the die flag. A first surface of a spacer mechanically and electrically couples to a first surface of the die flag, and a first surface of a die mechanically and electrically couples to a second surface of the spacer. At least one electrical connector electrically couples an electrical contact on a second surface of the die with a lead frame finger. A molding compound encapsulates the die, spacer, at least a portion of the at least one electrical connector, at least a portion of the die flag, and at least a portion of each lead frame finger. A width of the spacer along the second surface of the spacer is greater than a width of the die flag along the first surface of the die flag.
    Type: Application
    Filed: October 8, 2014
    Publication date: April 14, 2016
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atapol Prajuckamol, Jin Yoong Liong, Kai Chat Tan