Abstract: The present invention provides non-volatile memory cell transistors that have increased control-to-floating gate coupling coefficients due to a non-uniform gate surface area. In memory cells of the present invention, the floating gate is formed with a non-flat, non-uniform surface, which significantly increases the surface area interface between the floating gate and the inter-gate dielectric as well as the surface area interface between the inter-gate dielectric and the control gate. As a result, the inter-gate capacitance and the gate coupling coefficient are significantly increased. A high gate coupling coefficient allows the creation of small sized high performance memory cells that have high program and erase efficiency and read speed and can function at lower operation voltages. Higher gate coupling ratio allows also lowering operation voltages of memory cell which simplifies flash chip design, especially for lower power supply voltages.

Abstract: In one embodiment of the present invention, a method of forming semiconductor transistors includes: forming a gate electrode over but insulated from a semiconductor body region; forming off-set spacers along side-walls of the gate electrode; and after forming said off-set spacers, forming a source region and a drain region in the body region so that the extent of an overlap between the gate electrode and each of the source and drain regions is dependent on a thickness of the off-set spacers.

Abstract: A non-volatile memory device includes a substrate having a first active region and a second active region. A first floating gate is provided over the first active region and having an edge, the first floating gate being made of a conductive material. A first spacer is connected to the edge of the first floating gate and being made of the same conductive material as that of the first floating gate. A control gate is provided proximate to the floating gate.

Abstract: A method of erasing a non-volatile memory includes applying a first potential of first polarity to a control gate; applying a second potential of second polarity to a bulk region, the second potential being an N magnitude; and applying a third potential of second polarity to a source region, the third potential being an M magnitude, wherein the N and M are substantially the same.

Abstract: Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.

Abstract: In accordance with an embodiment of the present invention, a semiconductor structure includes an undoped polysilicon layer, a doped polysilicon layer in contact with the undoped polysilicon layer, and an insulating layer in contact with the undoped polysilicon layer. The undoped polysilicon layer is sandwiched between the doped polysilicon layer and the insulating layer.

Abstract: Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.

Abstract: Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.

Abstract: Structures and methods for flash memory transistors are formed with self-aligned drain/source contacts. The flash transistors are formed with a plurality of gate layers. An etch resistant layer(s) are deposited on top of the gate layers in the memory array transistors and on the gate layers of peripheral transistors. An additional oxide layer/spacer may be formed on the etch resistant layer to control the resulting transistor junction configuration. As a result within the same process various transistors may be formed satisfying various requirements. Contact holes to the drain and source regions of the memory and peripheral transistors are then formed. The etch resistant layer prevents the contact etchants from completely etching away the protective etch resistant layer surrounding the gate layers. The spacing between the drain/source contacts and the gate layers can be greatly reduced increasing the density of the memory array transistors and reducing chip size.

Abstract: In one embodiment of the present invention, a method of forming semiconductor transistors includes: forming a gate electrode over but insulated from a semiconductor body region; forming off-set spacers along side-walls of the gate electrode; and after forming said off-set spacers, forming a source region and a drain region in the body region so that the extent of an overlap between the gate electrode and each of the source and drain regions is dependent on a thickness of the off-set spacers.

Abstract: In one embodiment of the present invention, a method of forming semiconductor transistors includes: forming a gate electrode over but insulated from a semiconductor body region; forming off-set spacers along side-walls of the gate electrode; and after forming said off-set spacers, forming a source region and a drain region in the body region so that the extent of an overlap between the gate electrode and each of the source and drain regions is dependent on a thickness of the off-set spacers.