Patents by Inventor Kai-Chi Chen
Kai-Chi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9617411Abstract: An organic-inorganic hybrid resin, a molding composition, and a photoelectric device employing the same are disclosed. The organic-inorganic hybrid resin is a reaction product of a composition, wherein the composition includes: 0.1-10 parts by weight of reactant (a), and 100 parts by weight of reactant (b). In particular, the reactant (a) is a silsesquioxane prepolymer with metal oxide clusters, and the metal oxide cluster includes Ti, Zr, Zn, or a combination thereof. The reactant (b) includes an epoxy resin.Type: GrantFiled: January 14, 2015Date of Patent: April 11, 2017Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ying-Nan Chan, Shu-Chen Huang, Wen-Bin Chen, Kai-Chi Chen, Chih-Hao Lin, Hsun-Tien Li
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Patent number: 9540488Abstract: A siloxane resin and photoelectric device employing the same are provided. The siloxane resin composition includes (a) 45-87 parts by weight of a first siloxane compound represented by Formula (I), wherein each R1 is independently C1-3 alkyl group, and n is an integer from 2 to 15; (b) 5-35 parts by weight of a second siloxane compound represented by Formula (II), wherein each R2 and R3 are independently C1-3 alkyl group; each R4 is independently C1-3 alkyl group, or epoxy group; x?1, y?2, and x/y is from about 0.Type: GrantFiled: December 30, 2015Date of Patent: January 10, 2017Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-Hao Lin, Wen-Bin Chen, Ying-Nan Chan, Shu-Chen Huang, Kai-Chi Chen
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Publication number: 20150197631Abstract: An organic-inorganic hybrid resin, a molding composition, and a photoelectric device employing the same are disclosed. The organic-inorganic hybrid resin is a reaction product of a composition, wherein the composition includes: 0.1-10 parts by weight of reactant (a), and 100 parts by weight of reactant (b). In particular, the reactant (a) is a silsesquioxane prepolymer with metal oxide clusters, and the metal oxide cluster includes Ti, Zr, Zn, or a combination thereof. The reactant (b) includes an epoxy resin.Type: ApplicationFiled: January 14, 2015Publication date: July 16, 2015Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ying-Nan CHAN, Shu-Chen HUANG, Wen-Bin CHEN, Kai-Chi CHEN, Chih-Hao LIN, Hsun-Tien LI
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Patent number: 8013039Abstract: An encapsulant composition for a light-emitting diode is provided. One embodiment of the encapsulant composition comprises: (a) about 100 parts by weight of at least one liquid bi-functional epoxy resin containing about 40˜50 weight % of aromatic ring; (b) about 55˜120 parts by weight of a curing agent comprising at least one bi-functional thiol curing agent containing aromatic ring and at least one aliphatic tetra-functional thiol curing agent, wherein the curing agent contains about 10˜50 weight % of aromatic ring and about 20˜35 weight % of sulfur; and (c) about 0.05˜0.5 parts by weight of a catalyst. The encapsulant composition having a high refractive index can be used for a solid state light emitting device to enhance light extraction efficiency.Type: GrantFiled: June 27, 2008Date of Patent: September 6, 2011Assignee: Industrial Technology Research InstituteInventors: Chia-Wen Hsu, Hsun-Tien Li, Kai-Chi Chen
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Publication number: 20090093570Abstract: An encapsulant composition for a light-emitting diode is provided. One embodiment of the encapsulant composition comprises: (a) about 100 parts by weight of at least one liquid bi-functional epoxy resin containing about 40˜50 weight % of aromatic ring; (b) about 55˜120 parts by weight of a curing agent comprising at least one bi-functional thiol curing agent containing aromatic ring and at least one aliphatic tetra-functional thiol curing agent, wherein the curing agent contains about 10˜50 weight % of aromatic ring and about 20˜35 weight % of sulfur; and (c) about 0.05˜0.5 parts by weight of a catalyst. The encapsulant composition having a high refractive index can be used for a solid state light emitting device to enhance light extraction efficiency.Type: ApplicationFiled: June 27, 2008Publication date: April 9, 2009Inventors: Chia-Wen Hsu, Hsun-Tien Li, Kai-Chi Chen
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Patent number: 7230331Abstract: A chip package structure and a process for fabricating the same is disclosed. The chip package structure mainly comprises a carrier, a chip and an encapsulating material layer. To fabricate the chip package, a carrier and a plurality of chips are provided. Each chip has at least an active surface with a plurality of bumps thereon. The chips and the carrier are electrically connected. An encapsulating material layer that fills the bonding gap between the chips and the carriers and covers the chips and carrier is formed. The encapsulating material layer between the chips and the carrier has a first thickness and the encapsulating material layer over the chips has a second thickness. The second thickness has a value between half to twice the first thickness.Type: GrantFiled: January 5, 2004Date of Patent: June 12, 2007Assignees: Industrial Technology Research Institute, Matsushita Electric Works, Ltd.Inventors: Kai-Chi Chen, Shu-Chen Huang, Hsun-Tien Li, Tzong-Ming Lee, Taro Fukui, Tomoaki Nemoto
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Publication number: 20070072339Abstract: A process for fabricating a chip package structure is disclosed. To fabricate the chip package structure, a carrier and a plurality of chips are provided. Each chip has an active surface and at least one of the active surfaces has a plurality of bumps thereon. The chips and the carrier are electrically connected together. Thereafter, a heat sink is attached to the back of the chips and then at least one heat-resistant buffering film is formed over part of the heat sink surface. An encapsulating material layer is formed over the carrier and filling bonding gaps between the chips and the carrier. The encapsulating material within the bonding gaps has a thickness. The maximum diameter of particles constituting the encapsulating material layer is less than half of the said thickness.Type: ApplicationFiled: June 23, 2006Publication date: March 29, 2007Inventors: Kai-Chi Chen, Shu-Chen Huang, Hsun-Tien Li, Tzong-Ming Lee, Taro Fukui, Tomoaki Nemoto
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Publication number: 20060261499Abstract: A chip package structure and a process for fabricating the same is disclosed. The chip package structure mainly comprises a carrier, a chip and an encapsulating material layer. To fabricate the chip package, a carrier and a plurality of chips are provided. Each chip has at least an active surface with a plurality of bumps thereon. The chips and the carrier are electrically connected. An encapsulating material layer that fills the bonding gap between the chips and the carriers and covers the chips and carrier is formed. The encapsulating material layer between the chips and the carrier has a first thickness and the encapsulating material layer over the chips has a second thickness. The second thickness has a value between half to twice the first thickness.Type: ApplicationFiled: August 4, 2006Publication date: November 23, 2006Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, MATSUSHITA ELECTRIC WORKS, LTD.Inventors: Kai-Chi Chen, Shu-Chen Huang, Hsun-Tien Li, Tzong-Ming Lee, Taro Fukui, Tomoaki Nemoto
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Patent number: 7061103Abstract: A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is flip-chip bonded and electrically connected to the carrier or another chip. There is a flip-chip bonding gap between the chip and the carrier or other chips. A heat sink is positioned on the uppermost chip. The encapsulating material layer fills the flip-chip bonding gap as well as a gap between the uppermost chip and the heat sink. A part of the surface of the heat sink away from the upper-most chip is exposed. Furthermore, the encapsulating material layer is formed in a simultaneous molding process. For example, the chip is separated from the heat sink by a distance between 0.03˜0.2 mm, and the encapsulating material has a thermal conductivity greater than 1.2 W/m.K.Type: GrantFiled: January 5, 2004Date of Patent: June 13, 2006Assignees: Industrial Technology Research Institute, Matsushita Electric Works, Ltd.Inventors: Kai-Chi Chen, Shu-Chen Huang, Hsun-Tien Li, Tzong-Ming Lee, Taro Fukui, Tomoaki Nemoto
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Patent number: 7057277Abstract: A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is bonded and electrically connected to the carrier or another chip using a flip-chip bonding technique. A flip-chip bonding gap is set up between the chip and he carrier or other chips. The heat sink is set up over the top chip. The heat sink has an area bigger than the chip. The encapsulating material layer fills up the flip-chip bonding gap and covers the carrier as well as the heat sink. The encapsulating material layer is formed in a simultaneous molding process and has a thermal conductivity more than 1.2 W/m.K. Furthermore, a plurality of standoff components may be selectively positioned on the heat sink.Type: GrantFiled: January 5, 2004Date of Patent: June 6, 2006Assignees: Industrial Technology Research Institute, Matsushita Electric Works, Ltd.Inventors: Kai-Chi Chen, Shu-Chen Huang, Hsun-Tien Li, Tzong-Ming Lee, Taro Fukui, Tomoaki Nemoto
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Publication number: 20050087852Abstract: A chip package structure and a process for fabricating the same is disclosed. The chip package structure mainly comprises a carrier, a chip and an encapsulating material layer. To fabricate the chip package, a carrier and a plurality of chips are provided. Each chip has at least an active surface with a plurality of bumps thereon. The chips and the carrier are electrically connected. An encapsulating material layer that fills the bonding gap between the chips and the carriers and covers the chips and carrier is formed. The encapsulating material layer between the chips and the carrier has a first thickness and the encapsulating material layer over the chips has a second thickness. The second thickness has a value between half to twice the first thickness.Type: ApplicationFiled: January 5, 2004Publication date: April 28, 2005Inventors: Kai-Chi Chen, Shu-Chen Huang, Hsun-Tien Li, Tzong-Ming Lee, Taro FUKUI, Tomoaki NEMOTO
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Patent number: 6841094Abstract: Fine conductive particles are composed of metallic conductive powder, and an insulating organic capping layer on the grains of the powder. The metallic conductive powder have grains with a diameter ranging from 1 to 20 microns, and the capping layer has a thickness of 50-400 nm, which is able to flow by thermo-pressing. The insulating organic capping layer is prepared from a silane having a reactive functionality, a fluorine-containing silane and a compound or a resin having a functionality able to reactive with the reactive functionality.Type: GrantFiled: September 19, 2002Date of Patent: January 11, 2005Assignee: Industrial Technology Research InstituteInventors: Hsun-Tien Li, Shu-Chen Huang, Kai-Chi Chen
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Patent number: 6821818Abstract: A method of assembling a semiconductor device forming an encapsulant. The method includes providing a substrate having a plurality of semiconductor devices, respectively connecting a semiconductor chip electrically to a predetermined encapsulation area on a surface of the substrate, filling an encapsulant overlying the predetermined encapsulation area using stencil printing, sweeping excess encapsulant over the predetermined encapsulation area at a first air pressure below approximately 1 atm, sweeping encapsulant overlying the predetermined encapsulation area over the encapsulant overlying the predetermined encapsulation area using stencil printing at a second air pressure above the first air pressure, and hardening the encapsulant at a third air pressure above approximately 1 atm.Type: GrantFiled: July 14, 2003Date of Patent: November 23, 2004Assignee: Industrial Technology Research InstituteInventors: Kai-Chi Chen, Hsun-Tien Li
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Publication number: 20040212080Abstract: A chip package structure and a process for fabricating the same is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. To fabricate the chip package structure, a carrier and a plurality of chips are provided. Each chip has an active surface and at least one of the active surfaces has a plurality of bumps thereon. The chips and the carrier are electrically connected together. Thereafter, a heat sink is attached to the back of the chips and then at least one heat-resistant buffering film is formed over part of the heat sink surface. An encapsulating material layer is formed over the carrier and filling bonding gaps between the chips and the carrier. The encapsulating material within the bonding gaps has a thickness. The maximum diameter of particles constituting the encapsulating material layer is less than half of the said thickness.Type: ApplicationFiled: January 5, 2004Publication date: October 28, 2004Inventors: Kai-Chi Chen, Shu-Chen Huang, Hsun-Tien Li, Tzong-Ming Lee, Taro FUKUI, Tomoaki NEMOTO
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Publication number: 20040212056Abstract: A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is bonded and electrically connected to the carrier or another chip using a flip-chip bonding technique. A flip-chip bonding gap is set up between the chip and he carrier or other chips. The heat sink is set up over the top chip. The heat sink has an area bigger than the chip. The encapsulating material layer fills up the flip-chip bonding gap and covers the carrier as well as the heat sink. The encapsulating material layer is formed in a simultaneous molding process and has a thermal conductivity more than 1.2 W/m.K. Furthermore, a plurality of standoff components may be selectively positioned on the heat sink.Type: ApplicationFiled: January 5, 2004Publication date: October 28, 2004Inventors: Kai-Chi Chen, Shu-Chen Huang, Hsun-Tien Li, Tzong-Ming Lee, Taro FUKUI, Tomoaki NEMOTO
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Publication number: 20040212970Abstract: A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is flip-chip bonded and electrically connected to the carrier or another chip. There is a flip-chip bonding gap between the chip and the carrier or other chips. A heat sink is positioned on the uppermost chip. The encapsulating material layer fills the flip-chip bonding gap as well as a gap between the uppermost chip and the heat sink. A part of the surface of the heat sink away from the upper-most chip is exposed. Furthermore, the encapsulating material layer is formed in a simultaneous molding process. For example, the chip is separated from the heat sink by a distance between 0.03˜0.2 mm, and the encapsulating material has a thermal conductivity greater than 1.2 W/m.K.Type: ApplicationFiled: January 5, 2004Publication date: October 28, 2004Inventors: Kai-Chi Chen, Shu-Chen Huang, Hsun-Tien Li, Tzong-Ming Lee, Taro FUKUI, Tomoaki NEMOTO
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Publication number: 20040180472Abstract: A method of assembling a semiconductor device forming an encapsulant. The method includes providing a substrate having a plurality of semiconductor devices, respectively connecting a semiconductor chip electrically to a predetermined encapsulation area on a surface of the substrate, filling an encapsulant overlying the predetermined encapsulation area using stencil printing, sweeping excess encapsulant over the predetermined encapsulation area at a first air pressure below approximately 1 atm, sweeping encapsulant overlying the predetermined encapsulation area over the encapsulant overlying the predetermined encapsulation area using stencil printing at a second air pressure above the first air pressure, and hardening the encapsulant at a third air pressure above approximately 1 atm.Type: ApplicationFiled: July 14, 2003Publication date: September 16, 2004Applicant: Industrial Technology Research InstituteInventors: Kai-Chi Chen, Hsun-Tien Li
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Publication number: 20040056236Abstract: Fine conductive particles are composed of metallic conductive powder, and an insulating organic capping layer on the grains of the powder. The metallic conductive powder have grains with a diameter ranging from 1 to 20 microns, and the capping layer has a thickness of 50-400 nm, which is able to flow by thermo-pressing. The insulating organic capping layer is prepared from a silane having a reactive functionality, a fluorine-containing silane and a compound or a resin having a functionality able to reactive with the reactive functionality.Type: ApplicationFiled: September 19, 2002Publication date: March 25, 2004Applicant: Industrial Technology Research InstituteInventors: Hsun-Tien Li, Shu-Chen Huang, Kai-Chi Chen
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Patent number: 6627684Abstract: The present invention discloses a dielectric composition having two steps of laminating temperatures. The composition is comprised of: a diamine curing agent containing asymmetrical chemical structures with different reactivity; an epoxy resin compound, containing at least two epoxy groups; and inorganic powder. In addition, flame retardant and toughener are added dependent on the requirements.Type: GrantFiled: December 18, 2001Date of Patent: September 30, 2003Assignee: Industrial Technology Research InstituteInventors: Tzong-Ming Lee, Hsun-Tien Li, Kai-Chi Chen, Mei-Ling Chen
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Publication number: 20020123540Abstract: The present invention discloses a dielectric composition having two steps of laminating temperatures. The composition is comprised of: a diamine curing agent containing asymmetrical chemical structures with different reactivity; an epoxy resin compound, containing at least two epoxy groups; and inorganic powder. In addition, flame retardant and toughener are added dependent on the requirements.Type: ApplicationFiled: December 18, 2001Publication date: September 5, 2002Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Tzong-Ming Lee, Hsun-Tien Li, Kai-Chi Chen, Mei-Ling Chen