Patents by Inventor Kai-Chiang Wu

Kai-Chiang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11515274
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die laterally covered by an insulating encapsulation, a first redistribution structure disposed on the semiconductor die and the insulating encapsulation, a second redistribution structure disposed opposite to the first redistribution structure, and a through insulating via (TIV) penetrating through the insulating encapsulation. The semiconductor die is electrically coupled to the first redistribution structure through the second redistribution structure and the TIV. The first redistribution structure includes a patterned conductive layer covered by a patterned dielectric layer, and under-ball metallurgy (UBM) pattern partially covered by the patterned dielectric layer.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Yu Liang, Hsiu-Jen Lin, Kai-Chiang Wu, Chih-Chiang Tsao
  • Patent number: 11515173
    Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun Chen, Yu-Min Liang, Yen-Ping Wang, Jiun Yi Wu, Chen-Hua Yu, Kai-Chiang Wu
  • Patent number: 11509400
    Abstract: An image transmission system is disclosed. The image transmission system includes at least one image capturing device, at least one conversion device, at least one image processor, and at least one flexible printed circuit (FPC). The at least one FPC includes at least one conductive layer and at least one optical waveguide layer. The at least one image capturing device is configured to capture at least one data. The at least one conversion device is configured to perform a conversion between the at least one data and an optical signal. The at least one image processor is configured to obtain the at least one data according to the optical signal, and processes the data. The at least one optical waveguide layer is configured to transmit the optical signal.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: November 22, 2022
    Assignee: AuthenX Inc.
    Inventors: Po-Kuan Shen, Chao-Chieh Hsu, Chun-Chiang Yen, Chiu-Lin Yu, Kai-Lun Han, Sheng-Fu Lin, Jenq-Yang Chang, Mao-Jen Wu
  • Publication number: 20220359977
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Ping Wang, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Chung-Yi Hsu
  • Patent number: 11493711
    Abstract: A hybrid multi-layered optical flexible printed circuit device, comprising: an optical flexible substrate including a first open window and a second open window with a first, a second surfaces opposite to each other; an intrinsic film including a first bonding region aligned with the first open window and a second bonding region aligned with the second open window formed on the first surface; an optical waveguide film including a first notch with a first slant surface aligned with the first bonding region, and a second notch with a second slant surface aligned with the second bonding region formed on the second surface and encompassed the first open window and the second open window; a first flexible printed circuit board formed on the optical waveguide film; and a first optoelectronic device and a second optoelectronic device mounted in the first bonding region and the second bonding region of the intrinsic film.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: November 8, 2022
    Assignee: AuthenX Inc.
    Inventors: Po-Kuan Shen, Chao-Chieh Hsu, Sheng-Fu Lin, Chun-Chiang Yen, Chiu-Lin Yu, Kai-Lun Han, Jenq-Yang Chang, Mao-Jen Wu
  • Publication number: 20220342736
    Abstract: A data processing circuit and a fault-mitigating method are provided. In the method, multiple sub-sequences are divided from sequence data. A first sub-sequence of the sub-sequences is accessed from a memory for a multiply-accumulate (MAC) operation to obtain a first computed result. The MAC operation is performed on a second sub-sequence of the sub-sequences in the memory to obtain a second computed result. The first and the second computed results are combined, where the combined result of the first and the second computed results is related to the result of the MAC operation on the sequence data directly. Accordingly, the error rate could be reduced, so as to mitigate fault.
    Type: Application
    Filed: October 25, 2021
    Publication date: October 27, 2022
    Applicant: Skymizer Taiwan Inc.
    Inventors: Shu-Ming Liu, Jen-ho Kuo, Wen Li Tang, Kai-Chiang Wu
  • Publication number: 20220336385
    Abstract: A package includes a semiconductor package including a semiconductor die and a first insulating encapsulation, a substrate, and a second insulating encapsulation. The first insulating encapsulation encapsulates the semiconductor die. The substrate includes a redistribution circuitry, wherein the substrate is electrically coupled to the semiconductor package through the redistribution circuitry. The second insulating encapsulation is disposed on and partially covers the substrate, wherein the substrate is sandwiched between the semiconductor package and the second insulating encapsulation.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Publication number: 20220336386
    Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation. A method of manufacturing a package structure is also provided.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Han-Ping Pu, Yen-Ping Wang
  • Publication number: 20220320020
    Abstract: Provided is a package structure and a method of forming the same. The package structure includes a semiconductor package, a stacked patch antenna structure, and a plurality of conductive connectors. The semiconductor package includes a die. The stacked patch antenna structure is disposed on the semiconductor package, and separated from the semiconductor package by an air cavity. The plurality of conductive connectors is disposed in the air cavity between the semiconductor package and the stacked patch antenna structure to connect the semiconductor package and the stacked patch antenna structure.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 6, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yi Hsu, Kai-Chiang Wu, Yen-Ping Wang
  • Publication number: 20220320024
    Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 6, 2022
    Inventors: Hao-Hsiang Chuang, Shih-Wei Liang, Ching-Feng Yang, Kai-Chiang Wu, Hao-Yi Tsai, Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 11461204
    Abstract: A data processing circuit and a fault-mitigating method, which are adapted for a memory having a faulty bit, are provided. The memory is configured to store data related to an image, a weight for a multiply-accumulate (MAC) operation of image feature extraction, and/or a value for an activation operation. Sequence data is written into the memory. The bit number of the sequence data equals to the bit number used for storing data in a sequence block of the memory. The sequence data is accessed from the memory, wherein the access of the faulty bit in the memory is ignored. The value of the faulty bit is replaced by the value of a non-faulty bit in the memory to form new sequence data. The new sequence data is used for MAC. Accordingly, the accuracy of image recognition can be improved for the faulty memory.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: October 4, 2022
    Assignee: Skymizer Taiwan Inc.
    Inventors: Shu-Ming Liu, Kai-Chiang Wu, Wen Li Tang
  • Publication number: 20220285241
    Abstract: A method of forming a semiconductor package includes the following steps. A redistribution layer structure is formed over a first die and a dummy die, wherein the redistribution layer structure is directly electrically connected to the first die. An insulating layer is formed, wherein the insulating layer is disposed opposite to the redistribution layer structure with respect to the first die. At least one thermal through via is formed in the insulating layer.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Kuei Hsu, Ching-Feng Yang, Hsin-Yu Pan, Kai-Chiang Wu, Yi-Che Chiang
  • Publication number: 20220270944
    Abstract: Provided is a package structure and an antenna structure. The package structure includes a die; a first encapsulant, laterally encapsulating the die; a first redistribution structure, disposed on the first encapsulant and the die; a second encapsulant, disposed on the first redistribution structure; an antenna pattern, embedded in the second encapsulant and electrically connected to the first redistribution structure; and a dielectric layer, covering the antenna pattern, wherein an upper surface of the second encapsulant is exposed by the dielectric layer, and a laser mark is formed within the upper surface of the second encapsulant.
    Type: Application
    Filed: May 15, 2022
    Publication date: August 25, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Ta Lin, Chun-Lin Lu, Kai-Chiang Wu
  • Patent number: 11424197
    Abstract: A package includes a semiconductor package including a semiconductor die and a first insulating encapsulation, a substrate, and a second insulating encapsulation. The first insulating encapsulation encapsulates the semiconductor die. The substrate includes a redistribution circuitry, wherein the substrate is electrically coupled to the semiconductor package through the redistribution circuitry. The second insulating encapsulation is disposed on and partially covers the substrate, wherein the substrate is sandwiched between the semiconductor package and the second insulating encapsulation.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Publication number: 20220262734
    Abstract: A semiconductor package includes a redistribution layer structure, a first semiconductor chip, a circuit board structure and an encapsulation layer. The redistribution layer structure has a first side and a second side opposite to the first side. The first semiconductor chip is electrically connected to the first side of the redistribution layer structure. The circuit board structure is electrically connected to the first side of the redistribution layer structure, and the circuit board structure includes a first mask layer having an opening pattern that corresponds to first semiconductor chip. The encapsulation layer laterally encapsulates the circuit board structure and fills in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure.
    Type: Application
    Filed: May 4, 2022
    Publication date: August 18, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Chin-Liang Chen, Jiun-Yi Wu, Yen-Ping Wang
  • Patent number: 11417616
    Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation. A method of manufacturing a package structure is also provided.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: August 16, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chiang Wu, Han-Ping Pu, Yen-Ping Wang
  • Publication number: 20220254722
    Abstract: A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 11, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Publication number: 20220246521
    Abstract: A package component, a semiconductor package and a manufacturing method thereof are provided. The package component for electrically coupling a semiconductor die includes a functional circuit structure and a seal ring structure embedded in an insulating layer. The semiconductor die disposed on the package component is electrically coupled to the functional circuit structure. The seal ring structure is electrically isolated from the functional circuit structure, the seal ring structure includes a stack of alternating interconnect layers and via patterns, the via pattern at each level of the stack includes first features spaced apart from one another and arranged at neighboring corners of the insulating layer, and the first features are offset lengthwise relative to each other to overlap therewith, and the first features are spaced apart widthwise relative to each other.
    Type: Application
    Filed: April 11, 2022
    Publication date: August 4, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Yu Liang, Kai-Chiang Wu
  • Publication number: 20220246559
    Abstract: An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Inventors: Chung-Hao Tsai, Chia-Chia Lin, Kai-Chiang Wu, Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 11398422
    Abstract: A package structure including a redistribution circuit structure, a wiring substrate, an insulating encapsulation, a buffer layer, a semiconductor device and a stiffener ring is provided. The redistribution circuit structure includes a first surface and a second surface opposite to the first surface. The wiring substrate is disposed on the first surface of the redistribution circuit structure. The insulating encapsulation is disposed on the first surface of the redistribution circuit structure and laterally encapsulating the wiring substrate. The buffer layer is disposed over the second surface of the redistribution circuit structure. The semiconductor device is disposed on the buffer layer, and the semiconductor device is electrically connected to the wiring substrate through the redistribution circuit structure. The stiffener ring is adhered with the buffer layer by an adhesive.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Lin Lu, Jiun-Yi Wu, Kai-Chiang Wu