Patents by Inventor Kai-Chieh Chiu

Kai-Chieh Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250063720
    Abstract: A semiconductor device includes a substrate, an interconnect, a memory cell, and a plurality of first barrier structures. The interconnect is disposed over the substrate. The memory cell is disposed in the interconnect within a memory region of the substrate, where the memory cell includes a transistor and a capacitor. The transistor includes a gate, source/drain elements respectively standing at two opposite sides of the gate, and a channel disposed between the source/drain elements and overlapped with the gate. The capacitor is disposed over the transistor and electrically coupled to one of the source/drain elements. The plurality of first barrier structures line sidewalls and bottom surfaces of the source/drain elements, and each include a first barrier layer and a second barrier layer disposed between the source/drain elements and the first barrier layer, where a first absorption interface is disposed between the first barrier layer and the second barrier layer.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Che Lee, Huai-Ying Huang, Yen-Chieh Huang, Wei-Gang Chiu, Kai-Wen Cheng, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20250031388
    Abstract: A capacitor includes a bottom capacitor plate including a rough upper surface with a root mean square (RMS) surface roughness of at least 1.14, a capacitor dielectric layer on the bottom capacitor plate and contacting the rough upper surface of the bottom capacitor plate, and an upper capacitor plate on the capacitor dielectric layer. A semiconductor device includes a transistor located on a substrate, a dielectric layer on the transistor, and a capacitor in the dielectric layer and including a bottom capacitor plate connected to a source region of the transistor and having a rough upper surface with a root mean square (RMS) surface roughness of at least 1.14.
    Type: Application
    Filed: July 19, 2023
    Publication date: January 23, 2025
    Inventors: I-Che Lee, Pin-Ju Chen, Wei-Gang Chiu, Yen-Chieh Huang, Kai-Wen Cheng, Huai-Ying Huang, Yu-Ming Lin
  • Patent number: 11251697
    Abstract: A power converting device for power supply comprises an input port, a voltage boost circuit and an output port. Input port has an input standby pin configured to transmit a first power signal having a first voltage value and an input power pin configured to transmit a second power signal having a second voltage value. Voltage boost circuit electrically connecting to the input standby pin and receives and converts the first power signal having the first voltage value into the first power signal having the second voltage value. Output port has an output standby pin electrically connecting to the voltage boost circuit to receive the first power signal having the second voltage value and an output power pin electrically connecting to the input power pin to receive the second power signal having the second voltage value, wherein the second voltage value is higher than the first voltage value.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: February 15, 2022
    Assignees: MICRO-STAR INT'L CO., LTD., MSI COMPUTER (SHENZHEN) CO., LTD.
    Inventors: Kai-Chieh Chiu, Ming-Chih Lo, Chung-Hsing Chang