Patents by Inventor Kai Chirca

Kai Chirca has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160124890
    Abstract: The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.
    Type: Application
    Filed: October 31, 2014
    Publication date: May 5, 2016
    Inventors: David M. Thompson, Timothy Anderson, Joseph Zbiciak, Abhijeet A. Chachad, Kai Chirca, Matthew D. Pierson
  • Patent number: 9304925
    Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. Each processor has an associated return buffer allowing out of order responses of memory read data and cache snoop responses to ensure maximum bandwidth at the endpoints, and all endpoints receive status messages to simplify the return queue.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: April 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kai Chirca, Matthew D Pierson
  • Patent number: 9304954
    Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the endian view used by each individual processor within the attached subsystem, and can perform the appropriate endian conversion on each processor's transactions to adapt the transaction to/from the endian view used by the interconnect.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: April 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Daniel B Wu, Matthew D Pierson, Kai Chirca
  • Patent number: 9298665
    Abstract: This invention optimizes non-shared accesses and avoids dependencies across coherent endpoints to ensure bandwidth across the system even when sharing. The coherence controller is distributed across all coherent endpoints. The coherence controller for each memory endpoint keeps a state around for each coherent access to ensure the proper ordering of events. The coherence controller of this invention uses First-In-First-Out allocation to ensure full utilization of the resources before stalling and simplicity of implementation. The coherence controller provides Snoop Command/Response ID Allocation per memory endpoint.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: March 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Matthew D Pierson, Kai Chirca
  • Publication number: 20160062887
    Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace)in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.
    Type: Application
    Filed: November 11, 2015
    Publication date: March 3, 2016
    Inventors: Kai Chirca, Matthew D Pierson
  • Publication number: 20160055096
    Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.
    Type: Application
    Filed: November 3, 2015
    Publication date: February 25, 2016
    Inventors: Kai Chirca, Matthew D Pierson, Daniel B Wu, Timothy D Anderson
  • Patent number: 9239798
    Abstract: A prefetch cancelation arbiter improves access to a shared memory resource by arbitrarily canceling speculative prefetches. The prefetch cancelation arbiter applies a set of arbitrary policies to speculative prefetches to select one or more of the received speculative prefetches to cancel. The selected speculative prefetches are canceled and a cancelation notification of each canceled speculative prefetch is sent to a higher-level memory component such as a prefetch unit or a local memory arbiter that is local to the processor associated with the canceled speculative prefetch. The set of arbitrary policies is used to reduce memory accesses to the shared memory resource.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: January 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Matthew D Pierson, Joseph R M Zbiciak, Kai Chirca, Amitabh Menon, Timothy D Anderson
  • Publication number: 20150370710
    Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.
    Type: Application
    Filed: September 1, 2015
    Publication date: December 24, 2015
    Inventors: Daniel B. Wu, Matthew D. Pierson, Kai Chirca, Timothy D. Anderson
  • Patent number: 9213656
    Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: December 15, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kai Chirca, Matthew D Pierson
  • Patent number: 9208120
    Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: December 8, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kai Chirca, Matthew D. Pierson, Daniel B. Wu, Timothy D. Anderson
  • Patent number: 9152586
    Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: October 6, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Daniel B Wu, Matthew D Pierson, Kai Chirca, Timothy D Anderson
  • Patent number: 9129071
    Abstract: This invention speeds operation for coherence writes to shared memory. This invention immediately commits to the memory endpoint coherence write data. Thus this data will be available earlier than if the memory controller stalled this write pending snoop responses. This invention computes write enable strobes for the coherence write data based upon the cache dirty tags. This invention initiates a snoop cycle based upon the address of the coherence write. The stored write enable strobes enable determination of which data to write to the endpoint memory upon a cached and dirty snoop response.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: September 8, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Matthew D Pierson, Kai Chirca, Timothy D Anderson
  • Patent number: 9075928
    Abstract: A coherence maintenance address queue tracks each memory access from receipt until the memory reports the access complete. The address of each new access is compared against the address of all entries in the queue. This check is made when the access is ready to transmit to the memory. If there is no address match, then the current access does not conflict with any pending access. If there is an address match, the current access is stalled. The multi-core shared memory controller would then typically proceed to another access waiting a slot to the endpoint memory. Stored addresses in the coherence maintenance address queue are retired when the endpoint memory reports completion of the operation. At this point the access is no longer a hazard to following operations.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: July 7, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Matthew D Pierson, Kai Chirca
  • Patent number: 8977819
    Abstract: A prefetch filter receives a memory read request having an associated address for accessing data that is stored in a line of memory. An address window is determined that has an address range that encompasses an address space that is twice as large as the line of memory. In response to a determination of in which half the address window includes the requested line of memory, a prefetch direction is to a first direction or to an opposite direction. The prefetch filter can include an array of slots for storing a portion of a next predicted access and determine a memory stream in response to a hit on the array by a subsequent memory request. The prefetch filter FIFO counter cycles through the slots of the array before wrapping around to a first slot of the array for storing a next predicted address portion.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: March 10, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Kai Chirca, Joseph R M Zbiciak, Matthew D Pierson, Timothy D Anderson
  • Publication number: 20150019840
    Abstract: This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.
    Type: Application
    Filed: July 15, 2014
    Publication date: January 15, 2015
    Inventors: Timothy D. Anderson, Joseph Zbiciak, Duc Quang Bui, Abnijeet A. Chachad, Kai Chirca, Naveen Bhoria, Matthew D. Pierson, Daniel Wu
  • Patent number: 8880847
    Abstract: A prefetching system receives a memory read request having an associated address. In response to a determination that a most significant portion of the associated address is not present within slots of an array for storing the most significant portion of predicted addresses, a prefetch FIFO (First In-First Out) counter is modified to point to a next slot of the array and a new predicted address is generated in response to the received most significant portion of the associated address and is placed in the next slot of the array. The prefetch FIFO counter cycles through the slots of the array before wrapping around to a first slot of the array for storing the most significant portion of predicted addresses.
    Type: Grant
    Filed: July 4, 2011
    Date of Patent: November 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Kai Chirca
  • Publication number: 20140181165
    Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B?2k.
    Type: Application
    Filed: February 27, 2014
    Publication date: June 26, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Timothy D. Anderson, Mujibur Rahman, Kai Chirca
  • Publication number: 20140156951
    Abstract: This invention optimizes non-shared accesses and avoids dependencies across coherent endpoints to ensure bandwidth across the system even when sharing. The coherence controller is distributed across all coherent endpoints. The coherence controller for each memory endpoint keeps a state around for each coherent access to ensure the proper ordering of events. The coherence controller of this invention uses First-In-First-Out allocation to ensure full utilization of the resources before stalling and simplicity of implementation. The coherence controller provides Snoop Command/Response ID Allocation per memory endpoint.
    Type: Application
    Filed: October 22, 2013
    Publication date: June 5, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Matthew D. Pierson, Kai Chirca
  • Publication number: 20140149690
    Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.
    Type: Application
    Filed: October 24, 2013
    Publication date: May 29, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Kai Chirca, Matthew D. Pierson, Daniel B. Wu, Timothy D. Anderson
  • Publication number: 20140143849
    Abstract: This invention is a security firewall having a security hierarchy including: secure master (SM); secure guest (SG); and non-secure (NS). There is one secure master and n secure guests. The firewall includes one secure region for secure master and one secure region for secure guests. The SM region only allows access from the secure master and the SG region allows accesses from any secure transaction. Finally, the non-secure region can be implemented two ways. In a first option, non-secure regions may be accessed only upon non-secure transactions. In a second option, non-secure regions may be accessed any processing core. In this second option, the access is downgraded to a non-secure access if the security identity is secure master or secure guest. If the two security levels are not needed the secure master can unlock the SM region to allow any secure guest access to the SM region.
    Type: Application
    Filed: October 24, 2013
    Publication date: May 22, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Timothy D. Anderson, Joseph R. M. Zbiciak, Matthew D. Pierson, Kai Chirca