Patents by Inventor Kai-Chuan KAN
Kai-Chuan KAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230290884Abstract: A diode structure includes a substrate having a first conductivity type, a first well region having a second conductivity type opposite to the first conductivity type and disposed in the substrate, a first doped region having the first conductivity type and disposed in the first well region, a ring-shaped well region having the second conductivity type, disposed in the first well region and surrounding the first doped region, an anode disposed on the first doped region, a second well region having the second conductivity type, separated from the first well region and disposed in the substrate, a second doped region having the second conductivity type and disposed in the second well region, and a cathode disposed on the second doped region.Type: ApplicationFiled: March 14, 2022Publication date: September 14, 2023Applicant: Vanguard International Semiconductor CorporationInventors: Jing-Da Li, Kai-Chuan Kan, Chung-Ren Lao
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Patent number: 11742389Abstract: A method for forming a semiconductor structure includes providing a substrate including a first region with a first gate structure and a second region with a second gate structure. First to third dielectric layers are formed on the substrate. The third dielectric layer is patterned to form a first portion in the first region and a second portion in the second region. The second region is covered and at least a portion of the first portion is removed to form a first mask. The second dielectric layer is pattern by using the first mask and the second portion as the second mask to expose a portion of the first dielectric layer. The portion of the first dielectric layer is removed to form a first stacked spacer on the first gate structure and a second stacked spacer on the second gate structure.Type: GrantFiled: May 18, 2021Date of Patent: August 29, 2023Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Hung-Chih Tan, Hsing-Chao Liu, Chih-Cherng Liao, Hsiao-Ying Yang, Kai-Chuan Kan, Jing-Da Li
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Publication number: 20230231002Abstract: A semiconductor device includes a substrate, a first well region, a second well region, an isolation region, a first resistor segment and a second resistor segment. The substrate includes a region having a first conductivity type. The first and the second well regions are disposed in the region of the substrate. The isolation region is disposed on the first and the second well regions. The first and the second resistor segments are electrically connected to each other and disposed on the isolation region. Moreover, the first and the second well regions are disposed directly under the first and the second resistor segments, respectively. The first and the second well regions do not overlap with each other in a vertical projection direction and have a second conductivity type that is opposite to the first conductivity type.Type: ApplicationFiled: January 19, 2022Publication date: July 20, 2023Applicant: Vanguard International Semiconductor CorporationInventors: Yu-Jui Chang, Chien-Hsien Song, Kai-Chuan Kan
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Patent number: 11569121Abstract: Methods of forming semiconductor devices are provided. The methods include: forming a trench in a substrate, wherein the trench includes a defect protruding from a bottom surface of the trench; forming a flowable material on the substrate to at least partially cover the defect; performing an etching process to reduce the height of the defect; and removing the flowable material.Type: GrantFiled: May 26, 2021Date of Patent: January 31, 2023Assignee: Vanguard International Semiconductor CorporationInventors: I-Ping Lee, Kwang-Ming Lin, Chih-Cherng Liao, Ya-Huei Kuo, Pei-Yu Chang, Ya-Ting Chang, Tsung-Hsiung Lee, Zheng-Xian Wu, Kai-Chuan Kan, Yu-Jui Chang, Yow-Shiuan Liu
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Publication number: 20220384251Abstract: Methods of forming semiconductor devices are provided. The methods include: forming a trench in a substrate, wherein the trench includes a defect protruding from a bottom surface of the trench; forming a flowable material on the substrate to at least partially cover the defect; performing an etching process to reduce the height of the defect; and removing the flowable material.Type: ApplicationFiled: May 26, 2021Publication date: December 1, 2022Applicant: Vanguard International Semiconductor CorporationInventors: I-Ping LEE, Kwang-Ming LIN, Chih-Cherng LIAO, Ya-Huei KUO, Pei-Yu CHANG, Ya-Ting CHANG, Tsung-Hsiung LEE, Zheng-Xian WU, Kai-Chuan KAN, Yu-Jui CHANG, Yow-Shiuan LIU
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Publication number: 20220376052Abstract: A method for forming a semiconductor structure includes providing a substrate including a first region with a first gate structure and a second region with a second gate structure. First to third dielectric layers are formed on the substrate. The third dielectric layer is patterned to form a first portion in the first region and a second portion in the second region. The second region is covered and at least a portion of the first portion is removed to form a first mask. The second dielectric layer is pattern by using the first mask and the second portion as the second mask to expose a portion of the first dielectric layer. The portion of the first dielectric layer is removed to form a first stacked spacer on the first gate structure and a second stacked spacer on the second gate structure.Type: ApplicationFiled: May 18, 2021Publication date: November 24, 2022Applicant: Vanguard International Semiconductor CorporationInventors: Hung-Chih TAN, Hsing-Chao LIU, Chih-Cherng LIAO, Hsiao-Ying YANG, Kai-Chuan KAN, Jing-Da LI
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Publication number: 20200194581Abstract: A semiconductor device includes a semiconductor substrate, a buried layer disposed in the semiconductor substrate, and a first well region, a second well region, a third well region and a fourth well region disposed in the semiconductor substrate on the buried layer. The semiconductor device also includes a source region disposed in the second well region, a drain region disposed in the first well region, a gate structure disposed on the first well region and the second well region, and a deep trench isolation structure disposed in the semiconductor substrate and surrounding the source region and the drain region. The second well region surrounds the first well region. The third well region and the fourth well region are located on opposite sides of the second well region. The deep trench isolation structure penetrates through the buried layer.Type: ApplicationFiled: December 18, 2018Publication date: June 18, 2020Applicant: Vanguard International Semiconductor CorporationInventors: Kai-Chuan KAN, Shu-Wei HSU, Chien-Hsien SONG, Tzu-Hsuan CHEN