Patents by Inventor Kai-Chun Hsu

Kai-Chun Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250151433
    Abstract: A pixel array that includes some pixels with high absorption (HA) structures and other pixels without HA structures exhibits increased dynamic range for near infrared (NIR) light. Additionally, the pixel array is a uniform array of photodiodes and thus does not exhibit current leakage that would have been caused by irregular isolation structures. Additionally, the pixel array may further a lateral overflow integration capacitor to further increase the dynamic range for NIR light.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Inventors: Cheng-Ying HO, Kai-Chun HSU, Wen-De WANG, Yuh HUANG, Cheng-Yu HSIEH, Hung-Yu WANG, Jen-Cheng LIU
  • Publication number: 20250126914
    Abstract: An image sensor includes photosensitive areas in a first array within a semiconductor substrate. Microlens are disposed over the semiconductor substrate in a second array. Metal shields are disposed between a subset of the microlenses and corresponding photosensitive areas. The metal half-shields have dimensions and positions that provide half-shielding that enables half-shield phase detection autofocus. An antireflective coating is disposed over the metal half-shields. The metal half-shields and the antireflective coating may be in a composite grid that provides lateral separation between color filters. Alternatively, metal half-shields and the antireflective coating may be in below a layer that includes color filters. The antireflective coating includes a quarter-wave layer.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 17, 2025
    Inventors: Cheng Ying Ho, Kai-Chun Hsu, Wen-De Wang, Cheng-Yu Hsieh, Jen-Cheng Liu
  • Publication number: 20240429258
    Abstract: A process used to form a first deep trench isolation (DTI) structure in a pixel region of a semiconductor substrate is also used to form a second DTI structure in a guard ring area that isolates the pixel region from a peripheral region. The guard ring area may have a PNP guard ring structure. The second DTI structure may include trenches in each of an inner ring, a middle, and an outer ring of the PNP guard ring structure. The first and second DTI structures may have conductive cores. The conductive cores of the inner and outer ring may be biased to a first voltage while the conductive cores of the middle ring may be biased to an opposite polarity second voltage. When the second DTI structure have conductive cores with these biases, the second DTI structure may be used as the guard ring without the PNP structure.
    Type: Application
    Filed: June 26, 2023
    Publication date: December 26, 2024
    Inventors: Cheng-Ying Ho, Wen-De Wang, Kai-Chun Hsu, Yuh Ruey Huang, Chih-Lung Cheng, Jen-Cheng Liu
  • Patent number: 11996433
    Abstract: The present disclosure relates to a semiconductor structure. The semiconductor structure includes a dielectric layer having a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The dielectric layer defines a recess in the first dielectric surface, and the recess includes a sidewall of the dielectric layer. A first conductive layer contacts a bottom surface of the dielectric layer. The sidewall of the dielectric layer is directly over the first conductive layer. A second conductive layer contacts the first conductive layer and the dielectric layer. The second conductive layer vertically extends from the first conductive layer to above the dielectric layer. A third conductive layer contacts the second conductive layer. The third conductive layer is laterally separated from a sidewall of the second conductive layer that faces the third conductive layer by a non-zero distance.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chun Hsu, Ching-Chun Wang, Dun-Nian Yaung, Jeng-Shyan Lin, Shyh-Fann Ting
  • Patent number: 11837622
    Abstract: An image sensor includes a semiconductor substrate, a gate dielectric layer, a gate electrode, a protection oxide film, and a nitride hard mask. The gate dielectric layer is over the semiconductor substrate. The gate electrode is over the gate dielectric layer. An entirety of a first portion of the gate dielectric layer directly under the gate electrode is of uniform thickness. The protection oxide film is in contact with a top surface of the gate electrode. The gate dielectric layer extends beyond a sidewall of the protection oxide film. The nitride hard mask is in contact with a top surface of the protection oxide film.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Wei Chia, Chun-Hao Chou, Kai-Chun Hsu, Kuo-Cheng Lee, Shyh-Fann Ting
  • Publication number: 20230378221
    Abstract: The present disclosure relates to an image sensor integrated chip (IC). The image sensor IC includes one or more interconnects arranged within an inter-level dielectric (ILD) structure on a first side of a substrate. An image sensing element is arranged within the substrate. Sidewalls of the substrate form one or more trenches extending from a second side of the substrate to within the substrate on opposing sides of the image sensing element. A dielectric structure is arranged on the sidewalls of the substrate that form the one or more trenches. A conductive core is arranged within the one or more trenches and is laterally separated from the substrate by the dielectric structure. The conductive core is electrically coupled to the one or more interconnects.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 23, 2023
    Inventors: Cheng-Ying Ho, Wen-De Wang, Kai-Chun Hsu, Sung-En Lin, Yuh-Ruey Huang, Jen-Cheng Liu
  • Publication number: 20230326951
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed within a semiconductor substrate. A dielectric structure is disposed on a first side of the semiconductor substrate. An isolation structure extends from the dielectric structure into the first side of the semiconductor substrate. The isolation structure laterally wraps around the photodetector and comprises an upper portion disposed above the first side of the semiconductor substrate and directly contacting sidewalls of the dielectric structure. The isolation structure comprises a first material different from a second material of the dielectric structure.
    Type: Application
    Filed: July 11, 2022
    Publication date: October 12, 2023
    Inventors: Cheng-Ying Ho, Wen-De Wang, Keng-Yu Chou, Kai-Chun Hsu, Tzu-Hsuan Hsu, Jen-Cheng Liu
  • Publication number: 20230317758
    Abstract: An optical device with isolation structures and a method of fabricating the same are disclosed. The optical device includes a substrate having a first surface and a second surface opposite to the first surface, first and second radiation sensing devices disposed in the substrate, a first isolation structure disposed in the substrate. The first isolation structure has a first surface and a second surface opposite to the first surface. The optical device further includes a second isolation structure disposed in the substrate and on the first surface of the first isolation structure. The second isolation structure includes a metal structure and a dielectric layer surrounding the metal structure. The second isolation structure vertically extends over the first surface of the substrate.
    Type: Application
    Filed: August 2, 2022
    Publication date: October 5, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ying Ho, Kuan-Hua Lin, Keng-Yu Chou, Kai-Chun Hsu, Sung-En Lin, Wen-De Wang, Jen-Cheng Liu
  • Publication number: 20220384514
    Abstract: An image sensor includes a semiconductor substrate, a gate dielectric layer, a gate electrode, a protection oxide film, and a nitride hard mask. The gate dielectric layer is over the semiconductor substrate. The gate electrode is over the gate dielectric layer. An entirety of a first portion of the gate dielectric layer directly under the gate electrode is of uniform thickness. The protection oxide film is in contact with a top surface of the gate electrode. The gate dielectric layer extends beyond a sidewall of the protection oxide film. The nitride hard mask is in contact with a top surface of the protection oxide film.
    Type: Application
    Filed: July 29, 2022
    Publication date: December 1, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Wei CHIA, Chun-Hao CHOU, Kai-Chun HSU, Kuo-Cheng LEE, Shyh-Fann TING
  • Patent number: 11444116
    Abstract: A method includes depositing a gate dielectric layer over a substrate. A gate electrode layer, a protection oxide layer, and a hard mask are sequentially deposited over the gate dielectric layer. The gate electrode layer and the protection oxide layer are patterned by using the hard mask as an etching mask to form a gate structure over the gate dielectric layer. An etching process is performed to remove the hard mask and thin the protection oxide layer after forming the gate structure.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Wei Chia, Chun-Hao Chou, Kai-Chun Hsu, Kuo-Cheng Lee, Shyh-Fann Ting
  • Publication number: 20220254828
    Abstract: The present disclosure relates to a semiconductor structure. The semiconductor structure includes a dielectric layer having a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The dielectric layer defines a recess in the first dielectric surface, and the recess includes a sidewall of the dielectric layer. A first conductive layer contacts a bottom surface of the dielectric layer. The sidewall of the dielectric layer is directly over the first conductive layer. A second conductive layer contacts the first conductive layer and the dielectric layer. The second conductive layer vertically extends from the first conductive layer to above the dielectric layer. A third conductive layer contacts the second conductive layer. The third conductive layer is laterally separated from a sidewall of the second conductive layer that faces the third conductive layer by a non-zero distance.
    Type: Application
    Filed: April 26, 2022
    Publication date: August 11, 2022
    Inventors: Kai-Chun Hsu, Ching-Chun Wang, Dun-Nian Yaung, Jeng-Shyan Lin, Shyh-Fann Ting
  • Patent number: 11322540
    Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a plurality of interconnects within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has sidewalls connected to one or more upper surfaces of the passivation structure. A bond pad is arranged directly between the sidewalls of the passivation structure. An upper passivation layer is disposed over the passivation structure and the bond pad. The upper passivation layer extends from over an upper surface of the bond pad to within a recess in the upper surface of the bond pad.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chun Hsu, Ching-Chun Wang, Dun-Nian Yaung, Jeng-Shyan Lin, Shyh-Fann Ting
  • Patent number: 11222915
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of interconnect layers within a dielectric structure over an upper surface of a substrate. A passivation structure is formed over the dielectric structure. The passivation structure has sidewalls and a horizontally extending surface defining has a recess within an upper surface of the passivation structure. A bond pad is formed having a lower surface overlying the horizontally extending surface and one or more protrusions extending outward from the lower surface. The one or more protrusions extend through one or more openings within the horizontally extending surface to contact a first one of the plurality of interconnect layers. An upper passivation layer is deposited on sidewalls and an upper surface of the bond pad and on sidewalls and the upper surface of the passivation structure.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chun Hsu, Ching-Chun Wang, Dun-Nian Yaung, Jeng-Shyan Lin, Shyh-Fann Ting
  • Publication number: 20210118939
    Abstract: A method includes depositing a gate dielectric layer over a substrate. A gate electrode layer, a protection oxide layer, and a hard mask are sequentially deposited over the gate dielectric layer. The gate electrode layer and the protection oxide layer are patterned by using the hard mask as an etching mask to form a gate structure over the gate dielectric layer. An etching process is performed to remove the hard mask and thin the protection oxide layer after forming the gate structure.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 22, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Wei CHIA, Chun-Hao CHOU, Kai-Chun HSU, Kuo-Cheng LEE, Shyh-Fann TING
  • Publication number: 20210028219
    Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a plurality of interconnects within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has sidewalls connected to one or more upper surfaces of the passivation structure. A bond pad is arranged directly between the sidewalls of the passivation structure. An upper passivation layer is disposed over the passivation structure and the bond pad. The upper passivation layer extends from over an upper surface of the bond pad to within a recess in the upper surface of the bond pad.
    Type: Application
    Filed: October 14, 2020
    Publication date: January 28, 2021
    Inventors: Kai-Chun Hsu, Ching-Chun Wang, Dun-Nian Yaung, Jeng-Shyan Lin, Shyh-Fann Ting
  • Patent number: 10879305
    Abstract: An image sensor includes a semiconductor substrate, a gate dielectric layer over the semiconductor substrate, a gate electrode over the gate dielectric layer, and a protection oxide film in contact with a top surface of the gate electrode. A top surface of the protection oxide film is free from contact with a hard mask comprising nitrogen.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Wei Chia, Chun-Hao Chou, Kai-Chun Hsu, Kuo-Cheng Lee, Shyh-Fann Ting
  • Patent number: 10833119
    Abstract: The present disclosure relates to an integrated circuit having a bond pad with a relatively flat surface topography that mitigates damage to underlying layers. In some embodiments, the integrated circuit has a plurality of metal interconnect layers within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has a recess with sidewalls connecting a horizontal surface of the passivation structure to an upper surface of the passivation structure. A bond pad is arranged within the recess and has a lower surface overlying the horizontal surface. One or more protrusions extend outward from the lower surface through openings in the passivation structure to contact one of the metal interconnect layers. Arranging the bond pad within the recess and over the passivation structure mitigates stress to underlying layers during bonding without negatively impacting an efficiency of an image sensing element within the substrate.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chun Hsu, Ching-Chun Wang, Dun-Nian Yaung, Jeng-Shyan Lin, Shyh-Fann Ting
  • Publication number: 20190172870
    Abstract: An image sensor includes a semiconductor substrate, a gate dielectric layer over the semiconductor substrate, a gate electrode over the gate dielectric layer, and a protection oxide film in contact with a top surface of the gate electrode.
    Type: Application
    Filed: January 31, 2019
    Publication date: June 6, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Wei CHIA, Chun-Hao CHOU, Kai-Chun HSU, Kuo-Cheng LEE, Shyh-Fann TING
  • Patent number: 10204960
    Abstract: A method of fabricating polysilicon gate structure in an image sensor device includes depositing a gate dielectric layer on a surface of a substrate. Then a polysilicon layer is deposited over the gate dielectric layer. Next, a protection film is deposited over the polysilicon layer. A hard mask is formed over the protection film, and the polysilicon gate structure is patterned. Following that, the hard mask is stripped off. The protection film exhibits etching selectivity against the polysilicon layer and has a thickness of between 40 and 60 angstroms. The hard mask is removed by phosphoric acid solution wet etching process.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Wei Chia, Chun-Hao Chou, Kai-Chun Hsu, Kuo-Cheng Lee, Shyh-Fann Ting
  • Publication number: 20180331146
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of interconnect layers within a dielectric structure over an upper surface of a substrate. A passivation structure is formed over the dielectric structure. The passivation structure has sidewalls and a horizontally extending surface defining has a recess within an upper surface of the passivation structure. A bond pad is formed having a lower surface overlying the horizontally extending surface and one or more protrusions extending outward from the lower surface. The one or more protrusions extend through one or more openings within the horizontally extending surface to contact a first one of the plurality of interconnect layers. An upper passivation layer is deposited on sidewalls and an upper surface of the bond pad and on sidewalls and the upper surface of the passivation structure.
    Type: Application
    Filed: July 20, 2018
    Publication date: November 15, 2018
    Inventors: Kai-Chun Hsu, Ching-Chun Wang, Dun-Nian Yaung, Jeng-Shyan Lin, Shyh-Fann Ting