Abstract: In a sophisticated semiconductor device including a large memory portion, a built-in self-test circuitry comprises a failure capturing logic that allows the capturing of a bitmap at a given instant in time without being limited to specific operating conditions in view of interfacing with external test equipment. Thus, although pipeline processing may be required due to the high speed operation during the self-test, reliable capturing of the bitmap may be achieved while maintaining high fault coverage of the test algorithm under consideration.

Abstract: In a sophisticated semiconductor device including a large memory portion, a built-in self-test circuitry comprises a failure capturing logic that allows the capturing of a bitmap at a given instant in time without being limited to specific operating conditions in view of interfacing with external test equipment. Thus, although pipeline processing may be required due to the high speed operation during the self-test, reliable capturing of the bitmap may be achieved while maintaining high fault coverage of the test algorithm under consideration.

Abstract: By providing at least two hardware representations of a specified circuit design, an efficient debugging system is provided that allows 100% design visibility at an extremely reduced simulation time owing to a time-shifted operation of the at least two hardware representations. Upon detection of a specified abort state in the leading hardware representation, the corresponding delayed state of the time-shifted hardware representation may be used for a subsequent simulation of only a relevant portion of the test run that has lead to the specified abort state.

Abstract: A device testing apparatus and method for testing a semiconductor device is provided. For device testing, stimulus data is generated and provided to the semiconductor device, and output data of the semiconductor device is then evaluated to verify proper operation of the semiconductor device. Further, data in the semiconductor device output data space is mapped to stimulus data, and a set of stimulus data is determined based on the mapping results for further testing.

Abstract: By providing at least two hardware representations of a specified circuit design, an efficient debugging system is provided that allows 100% design visibility at an extremely reduced simulation time owing to a time-shifted operation of the at least two hardware representations. Upon detection of a specified abort state in the leading hardware representation, the corresponding delayed state of the time-shifted hardware representation may be used for a subsequent simulation of only a relevant portion of the test run that has lead to the specified abort state.