Patents by Inventor Kai-Fa Ho

Kai-Fa Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240019789
    Abstract: A reticle is pre-heated prior to an exposure operation of a semiconductor substrate lot to reduce substrate to substrate temperature variations of the reticle in the exposure operation. The reticle may be pre-heated while being stored in a reticle storage slot, while being transferred from the reticle storage slot to a reticle stage of an exposure tool, and/or in another location prior to being secured to the reticle stage for the exposure operation. In this way, the reduction in temperature variation of the reticle in the exposure operation provided by pre-heating the reticle may reduce overlay deltas and misalignment for the semiconductor substrates that are processed in the exposure operation. This increases overlay performance, increases yield of the exposure tool, and increases semiconductor device quality.
    Type: Application
    Filed: August 9, 2023
    Publication date: January 18, 2024
    Inventors: Kai-Chieh CHANG, Kai-Fa HO, Li-Jui CHEN, Heng-Hsin LIU
  • Publication number: 20230384688
    Abstract: Some implementations described herein provide an exposure tool and associated methods of operation in which a scanner control system generates a scanner route for an exposure recipe such that the distance traveled by a substrate stage of the exposure tool along the scanner route is reduced and/or optimized for non-exposure fields on a semiconductor substrate. In this way, the scanner control system increases the productivity of the exposure tool, reduces processing times of the exposure tool, and increases yield in a semiconductor fabrication facility in which the exposure tool is included.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Kai-Chieh CHANG, Kai-Fa HO, Li-Jui CHEN, Heng-Hsin LIU
  • Patent number: 11822256
    Abstract: A reticle is pre-heated prior to an exposure operation of a semiconductor substrate lot to reduce substrate to substrate temperature variations of the reticle in the exposure operation. The reticle may be pre-heated while being stored in a reticle storage slot, while being transferred from the reticle storage slot to a reticle stage of an exposure tool, and/or in another location prior to being secured to the reticle stage for the exposure operation. In this way, the reduction in temperature variation of the reticle in the exposure operation provided by pre-heating the reticle may reduce overlay deltas and misalignment for the semiconductor substrates that are processed in the exposure operation. This increases overlay performance, increases yield of the exposure tool, and increases semiconductor device quality.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chieh Chang, Kai-Fa Ho, Li-Jui Chen, Heng-Hsin Liu
  • Patent number: 11809087
    Abstract: Some implementations described herein provide an exposure tool and associated methods of operation in which a scanner control system generates a scanner route for an exposure recipe such that the distance traveled by a substrate stage of the exposure tool along the scanner route is reduced and/or optimized for non-exposure fields on a semiconductor substrate. In this way, the scanner control system increases the productivity of the exposure tool, reduces processing times of the exposure tool, and increases yield in a semiconductor fabrication facility in which the exposure tool is included.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: November 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chieh Chang, Kai-Fa Ho, Li-Jui Chen, Heng-Hsin Liu
  • Publication number: 20220357676
    Abstract: A reticle is pre-heated prior to an exposure operation of a semiconductor substrate lot to reduce substrate to substrate temperature variations of the reticle in the exposure operation. The reticle may be pre-heated while being stored in a reticle storage slot, while being transferred from the reticle storage slot to a reticle stage of an exposure tool, and/or in another location prior to being secured to the reticle stage for the exposure operation. In this way, the reduction in temperature variation of the reticle in the exposure operation provided by pre-heating the reticle may reduce overlay deltas and misalignment for the semiconductor substrates that are processed in the exposure operation. This increases overlay performance, increases yield of the exposure tool, and increases semiconductor device quality.
    Type: Application
    Filed: August 27, 2021
    Publication date: November 10, 2022
    Inventors: Kai-Chieh CHANG, Kai-Fa HO, Li-Jui CHEN, Heng-Hsin LIU
  • Publication number: 20220350264
    Abstract: An exposure tool is configured to remove contaminants and/or prevent contamination of mirrors and/or other optical components included in the exposure tool. In some implementations, the exposure tool is configured to flush and/or otherwise remove contaminants from an illuminator, a projection optics box, and/or one or more other subsystems of the exposure tool using a heated gas such as ozone (O3) or extra clean dry air (XCDA), among other examples. In some implementations, the exposure tool is configured to provide a gas curtain (or gas wall) that includes hydrogen (H2) or another type of gas to reduce the likelihood of contaminants reaching the mirrors included in the exposure tool. In this way, the mirrors and one or more other components of the exposure tool are cleaned and maintained in a clean environment in which radiation absorbing contaminants are controlled to increase the performance of the exposure tool.
    Type: Application
    Filed: August 27, 2021
    Publication date: November 3, 2022
    Inventors: Kai-Chieh CHANG, Che-Chang HSU, Yen-Shuo SU, Chun-Lin CHANG, Kai-Fa HO, Li-Jui CHEN, Heng-Hsin LIU
  • Publication number: 20220350259
    Abstract: Some implementations described herein provide an exposure tool and associated methods of operation in which a scanner control system generates a scanner route for an exposure recipe such that the distance traveled by a substrate stage of the exposure tool along the scanner route is reduced and/or optimized for non-exposure fields on a semiconductor substrate. In this way, the scanner control system increases the productivity of the exposure tool, reduces processing times of the exposure tool, and increases yield in a semiconductor fabrication facility in which the exposure tool is included.
    Type: Application
    Filed: August 27, 2021
    Publication date: November 3, 2022
    Inventors: Kai-Chieh CHANG, Kai-Fa HO, Li-Jui CHEN, Heng-Hsin LIU
  • Patent number: 11195743
    Abstract: A stage for supporting a semiconductor substrate is disclosed. The stage includes a platform that defines a plurality of apertures, and a plurality of burls that protrude from the apertures, where the plurality of burls have support surfaces for supporting a region of the semiconductor substrate. The stage includes an actuator coupled to at least a first burl included in the plurality of burls, wherein the actuator is operable to adjust an elevation of a first support surface of the first burl relative to the platform, and control circuitry that controls operation of the actuator to establish a substantially-planar alignment of the support surface of the first burl with a support surface of at least a second burl included in the plurality of burls.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: December 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Ching-Hua Chen, Kai-Fa Ho
  • Publication number: 20210066114
    Abstract: A stage for supporting a semiconductor substrate is disclosed. The stage includes a platform that defines a plurality of apertures, and a plurality of burls that protrude from the apertures, where the plurality of burls have support surfaces for supporting a region of the semiconductor substrate. The stage includes an actuator coupled to at least a first burl included in the plurality of burls, wherein the actuator is operable to adjust an elevation of a first support surface of the first burl relative to the platform, and control circuitry that controls operation of the actuator to establish a substantially-planar alignment of the support surface of the first burl with a support surface of at least a second burl included in the plurality of burls.
    Type: Application
    Filed: July 17, 2020
    Publication date: March 4, 2021
    Inventors: Ching-Hua CHEN, Kai-Fa HO
  • Patent number: 9574875
    Abstract: A system includes a wafer stage adapted to hold a semiconductor wafer thereon. A moveable temperature sensor array is configured to move to a plurality of different positions over a surface of the wafer stage and to take a plurality of temperature measurements at the plurality of positions, respectively. Based on the plurality of temperature measurements, a controller is adapted to determine an expected thermal deformation for the semiconductor wafer or for a reticle arranged over the semiconductor wafer.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsun Lee, Kai-Fa Ho
  • Publication number: 20150204665
    Abstract: A system includes a wafer stage adapted to hold a semiconductor wafer thereon. A moveable temperature sensor array is configured to move to a plurality of different positions over a surface of the wafer stage and to take a plurality of temperature measurements at the plurality of positions, respectively. Based on the plurality of temperature measurements, a controller is adapted to determine an expected thermal deformation for the semiconductor wafer or for a reticle arranged over the semiconductor wafer.
    Type: Application
    Filed: January 21, 2014
    Publication date: July 23, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsun Lee, Kai-Fa Ho
  • Patent number: 8616539
    Abstract: The present disclosure relates to a wafer chuck configured to provide a uniform photoresist layer on a workpiece. In some embodiments, the wafer chuck comprises a plurality of vacuum holes. The plurality of vacuum holes (i.e., more than one) are in fluid communication with a cavity that continuously extends along the top surface between the vacuum holes. A vacuum source, connected to each vacuum hole, is configured to remove gas molecules from the cavity located below the workpiece leaving behind a low pressure vacuum. The use of a plurality of vacuum holes increase the uniformity of the vacuum, thereby preventing the formation of high vacuum areas in close proximity to any specific vacuum hole. The reduction of high vacuum areas reduces wafer bending associated with the high vacuum areas.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: December 31, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Hsiang Tseng, Jui-Chun Peng, Kai-Fa Ho, Ho-Ping Chen, Chia-Yun Lee
  • Publication number: 20130156947
    Abstract: The present disclosure relates to a wafer chuck configured to provide a uniform photoresist layer on a workpiece. In some embodiments, the wafer chuck comprises a plurality of vacuum holes. The plurality of vacuum holes (i.e., more than one) are in fluid communication with a cavity that continuously extends along the top surface between the vacuum holes. A vacuum source, connected to each vacuum hole, is configured to remove gas molecules from the cavity located below the workpiece leaving behind a low pressure vacuum. The use of a plurality of vacuum holes increase the uniformity of the vacuum, thereby preventing the formation of high vacuum areas in close proximity to any specific vacuum hole. The reduction of high vacuum areas reduces wafer bending associated with the high vacuum areas.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Hsiang Tseng, Jui-Chun Peng, Kai-Fa Ho, Ho-Ping Chen, Chia-Yun Lee