Patents by Inventor Kai Fan

Kai Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11183951
    Abstract: A flexure stage with modularized flexure units for convenient manufacturing, assembly and repair is provided. The flexure stage comprises a base, a platform separated from the base, and a plurality of flexure units disposed between the base and the platform. Each flexure unit comprises a first section, a second section, and a third section. The first section is located on the base. The second section is connected with the platform and separated from the first section. The third section is coupled with the first section and the second section through the first bending part and the second bending part respectively wherein the first bending part and the second bending part comprises flexibility in different axial directions.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: November 23, 2021
    Assignee: HIWIN MTKROSYSTEM CORP.
    Inventors: Chun-Hsiang Li, Chih-Kai Fan, Yu-Jung Chang
  • Publication number: 20210355932
    Abstract: An analysis method of absolute energy efficiency and relative energy efficiency of the compressed air system. For the compressed air system operating in a form of a single compressor, a gas flow rate and a corresponding operating power of the compressor operating in the single compressor model are measured under a specified flow rate. Meanwhile, influencing factors of the compressor operation are monitored. The absolute energy efficiency of the compressor is defined, and a curve of the absolute energy efficiency of the compressor varying with the operating time versus the above factors are plotted in a same coordinate system. Obtaining absolute energy efficiency data of the compressor in a corresponding state. By analyzing the absolute energy efficiency under corresponding conditions and based on the corresponding chart, the actual unit consumption of a given single compressor and its changing rule under different production and environmental operating conditions can be intuitively analyzed.
    Type: Application
    Filed: July 29, 2021
    Publication date: November 18, 2021
    Inventors: Xiaohua Wang, Chaoyang Zhai, Kai Zhao, Qi Lu, Zhongcai Tang, Xiang Fan
  • Patent number: 11171557
    Abstract: A power converter includes a full-bridge conversion circuit. The full-bridge conversion circuit includes a first leg and a second leg. The first leg includes at least two switches coupled to each other at a first node, and the second leg includes at least two switches coupled to each other at a second node. The power converter further includes an AC filter. The AC filter includes a first inductor, a second inductor and a capacitor. The first inductor includes a first end coupled to the first node and a second end could be couple to a grid. The second inductor includes a first end coupled to the second node and a second end could be couple to the grid. The capacitor includes a first end coupled to the second end of the first inductor and a second end coupled to the second leg. The first end of the capacitor is electrically coupled to the second end of the first inductor during a cycle of an AC voltage of the grid.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: November 9, 2021
    Assignee: ABB Schweiz AG
    Inventors: Sheng Zong, Guoxing Fan, Kai Tian, Mei Liang
  • Patent number: 11164979
    Abstract: A semiconductor device includes a semiconductor substrate, a Schottky layer, a plurality of first doped regions, a plurality of second doped regions, a first conductive layer and a second conductive layer. The semiconductor substrate includes a first conductive type, and the Schottky layer is disposed on the semiconductor substrate. The first doped regions and the second doped regions include a second conductive type, and which are disposed within the semiconductor substrate. The first doped regions are in parallel and extended along a first direction, and the second doped regions are in parallel and extended along a second direction to cross the first doped regions, thereby to define a plurality of grid areas. The first conductive layer is disposed on the Schottky layer, and the second conductive layer is disposed under the semiconductor substrate.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: November 2, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Kai-Chieh Hsu, Chun-Chih Chen, Li-Fan Chen, Ching-Ho Li, Ting-You Lin, Gong-Kai Lin, Yeh-Ning Jou, Chien-Hsien Song, Hsiao-Ying Yang, Chien-Chi Hsu, Fu-Chun Tseng
  • Patent number: 11151571
    Abstract: A computer-implement method of processing resource exchange information includes the following steps: obtaining a data package including a user card identifier and a social network application identifier from a mobile phone; establishing a correspondence between the user card identifier and the social network application identifier and storing the correspondence in the computer system; obtaining user card data and resource exchange information from a payment terminal, wherein the user card data includes the user card identifier; performing security verification to the user card data and obtaining the corresponding social network application identifier when the security verification succeeds; processing a resource transfer request according to the social network application identifier and the resource exchange information and generating corresponding processing state information; and returning the corresponding processing state information to the payment terminal.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: October 19, 2021
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Kai Liu, Liangliang Fan, Leteng Weng, Yaxuan Zhu
  • Patent number: 11119416
    Abstract: A method includes forming a first overlay feature in a first dielectric layer over a first wafer; forming a second dielectric layer over the first overlay feature and the first dielectric layer; forming an opening in the second dielectric layer by at least using an exposure tool; forming a second overlay feature in the opening of the second dielectric layer, such that a first edge of the first overlay feature is covered by the second dielectric layer; directing an electron beam to the first and second overlay features and the second dielectric layer; detecting the electron beam reflected from the first overlay feature through the second dielectric layer and from the second overlay feature by a detector; obtaining, by a controller, an overlay error between the first overlay feature and the second overlay feature according to the reflected electron beam electrically connected to the detector.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Yuan Sun, Yen-Liang Chen, He Fan, Yen-Hung Chen, Kai Lin
  • Patent number: 11094579
    Abstract: A method of forming a semiconductor structure includes depositing a mask layer over a substrate. The method includes etching the substrate to define a first opening. The method includes depositing a sacrificial material in the first opening. The method includes depositing a dielectric liner along sidewalls of the first opening, wherein a bottom surface of the dielectric liner contacts the sacrificial material. The method includes removing the sacrificial material. The method includes etching the substrate to enlarge the first opening to define a second opening. The second opening includes a first portion extending a first depth from the dielectric material in a first direction perpendicular to a top surface of the substrate, and a second portion extending in a second direction, parallel to the top surface of the substrate. The method includes removing the dielectric liner. The method includes filling the second opening with a dielectric material.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Bin Huang, Chien-Mao Chen, Yu-Hsuan Kuo, Shih-Kai Fan, Chia-Hung Lai, Kang-Min Kuo
  • Publication number: 20210130331
    Abstract: Synthesis of O-benzotriazole and O-imidazole synthons are described. Uses of synthons in synthesis of azapeptides and other peptidomimetics, azapeptides and other peptidomimetics synthesized from the synthons and uses of azapeptides and other peptidomimetics are also described.
    Type: Application
    Filed: January 7, 2021
    Publication date: May 6, 2021
    Applicant: THE FEINSTEIN INSTITUTES FOR MEDICAL RESEARCH
    Inventors: Yousef Al-Abed, Kai Fan Cheng
  • Patent number: 10979436
    Abstract: A policy associated with a notification received by one or more computer systems is obtained. A first request is submitted, to a service, for a first current capacity of a resource. An amount by which to adjust a capacity of the resource is calculated, based at least in part on the policy and the first current capacity. A second request is submitted, to the service, to adjust the capacity of the resource by the amount. A third request is submitted, to the service, for a second current capacity of the resource, and whether the second request has been fulfilled is determined based at least in part on a comparison between the second current capacity and the response to the third request.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 13, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Christopher Thomas Lewis, Kai Fan Tang, Farzad Moghimi, Ahmed Usman Khalid, Stephan Weinwurm
  • Patent number: 10919882
    Abstract: Synthesis of O-benzotriazole and O-imidazole synthons are described. Uses of synthons in synthesis of azapeptides and other peptidomimetics, azapeptides and other peptidomimetics synthesized from the synthons and uses of azapeptides and other peptidomimetics are also described.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: February 16, 2021
    Assignee: THE FEINSTEIN INSTITUTES FOR MEDICAL RESEARCH
    Inventors: Yousef Al-Abed, Kai Fan Cheng
  • Publication number: 20200354344
    Abstract: Synthesis of O-benzotriazole and O-imidazole synthons are described. Uses of synthons in synthesis of azapeptides and other peptidomimetics, azapeptides and other peptidomimetics synthesized from the synthons and uses of azapeptides and other peptidomimetics are also described.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 12, 2020
    Applicant: THE FEINSTEIN INSTITUTES FOR MEDICAL RESEARCH
    Inventors: Yousef Al-Abed, Kai Fan Cheng
  • Publication number: 20200301740
    Abstract: Techniques are described for optimizing the allocation of computing resources provided by a service provider network—for example, compute resources such as virtual machine (VM) instances, containers, standalone servers, and possibly other types of computing resources—among computing workloads associated with a user or group of users of the service provider network. A service provider network provides various tools and interfaces to help businesses and other organizations optimize the utilization of computing resource pools obtained by the organizations from the service provider network, including the ability to efficiently schedule use of the resources among workloads having varying resource demands, usage patterns, relative priorities, execution deadlines, or combinations thereof. A service provider network further provides various graphical user interfaces (GUIs) to help users visualize and manage the historical and scheduled uses of computing resources by users' workloads according to user preferences.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Inventors: Jacob Adam GABRIELSON, Joshua M. BURGIN, Brad BONNETT, Kai Fan TANG
  • Publication number: 20200301741
    Abstract: Techniques are described for optimizing the allocation of computing resources provided by a service provider network—for example, compute resources such as virtual machine (VM) instances, containers, standalone servers, and possibly other types of computing resources—among computing workloads associated with a user or group of users of the service provider network. A service provider network provides various tools and interfaces to help businesses and other organizations optimize the utilization of computing resource pools obtained by the organizations from the service provider network, including the ability to efficiently schedule use of the resources among workloads having varying resource demands, usage patterns, relative priorities, execution deadlines, or combinations thereof. A service provider network further provides various graphical user interfaces (GUIs) to help users visualize and manage the historical and scheduled uses of computing resources by users' workloads according to user preferences.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Inventors: Jacob Adam GABRIELSON, Joshua M. BURGIN, Brad BONNETT, Kai Fan TANG
  • Publication number: 20200301723
    Abstract: Techniques are described for optimizing the allocation of computing resources provided by a service provider network—for example, compute resources such as virtual machine (VM) instances, containers, standalone servers, and possibly other types of computing resources—among computing workloads associated with a user or group of users of the service provider network. A service provider network provides various tools and interfaces to help businesses and other organizations optimize the utilization of computing resource pools obtained by the organizations from the service provider network, including the ability to efficiently schedule use of the resources among workloads having varying resource demands, usage patterns, relative priorities, execution deadlines, or combinations thereof. A service provider network further provides various graphical user interfaces (GUIs) to help users visualize and manage the historical and scheduled uses of computing resources by users' workloads according to user preferences.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Inventors: Jacob Adam GABRIELSON, Joshua M. BURGIN, Brad BONNETT, Kai Fan TANG
  • Publication number: 20200286774
    Abstract: A method of forming a semiconductor structure includes depositing a mask layer over a substrate. The method includes etching the substrate to define a first opening. The method includes depositing a sacrificial material in the first opening. The method includes depositing a dielectric liner along sidewalls of the first opening, wherein a bottom surface of the dielectric liner contacts the sacrificial material. The method includes removing the sacrificial material. The method includes etching the substrate to enlarge the first opening to define a second opening. The second opening includes a first portion extending a first depth from the dielectric material in a first direction perpendicular to a top surface of the substrate, and a second portion extending in a second direction, parallel to the top surface of the substrate. The method includes removing the dielectric liner. The method includes filling the second opening with a dielectric material.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: Yen-Bin HUANG, Chien-Mao CHEN, Yu-Hsuan KUO, Shih-Kai FAN, Chia-Hung LAI, Kang-Min KUO
  • Publication number: 20200246924
    Abstract: A flexure stage with modularized flexure units for convenient manufacturing, assembly and repair is provided. The flexure stage comprises a base, a first carrier, a plurality of first flexure units, a gantry unit, a second carrier, and a plurality of second flexure units. The first carrier is separated from the base and reciprocated along a first axis. The first flexure units are disposed between the base and the first carrier wherein each of the first flexure units comprises flexibility in the first axis. The gantry unit is located on the base and separated from the first carrier. The second carrier is set on the gantry unit and reciprocated along a second axis. The second flexure units are disposed between the first carrier and the second carrier wherein each of the second flexure units comprises flexibility in the second axis.
    Type: Application
    Filed: February 5, 2019
    Publication date: August 6, 2020
    Inventors: Chun-Hsiang LI, Chih-Kai FAN, Yu-Jung CHANG
  • Publication number: 20200252008
    Abstract: A flexure stage with modularized flexure units for convenient manufacturing, assembly and repair is provided. The flexure stage comprises a base, a platform separated from the base, and a plurality of flexure units disposed between the base and the platform. Each flexure unit comprises a first section, a second section, and a third section. The first section is located on the base. The second section is connected with the platform and separated from the first section. The third section is coupled with the first section and the second section through the first bending part and the second bending part 35 respectively wherein the first bending part and the second bending part comprises flexibility in different axial directions.
    Type: Application
    Filed: February 5, 2019
    Publication date: August 6, 2020
    Inventors: Chun-Hsiang LI, Chih-Kai FAN, Yu-Jung CHANG
  • Patent number: 10699938
    Abstract: A semiconductor structure includes a shallow trench isolation (STI) structure. The semiconductor structure includes a substrate having a first surface. A STI structure extends from the first surface into the substrate. The STI structure includes a first portion and a second portion. The first portion extends from the first surface into the substrate, and has an intersection with the first surface. The second portion extends away from the first portion, and has a tip at a distance away from the intersection in a direction parallel to the first surface. The first portion and the second portion are filled with a dielectric material.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Bin Huang, Chien-Mao Chen, Yu-Hsuan Kuo, Shih-Kai Fan, Chia-Hung Lai, Kang-Min Kuo
  • Patent number: 10634649
    Abstract: A clamping apparatus for coupling an ultrasonic transducer to a conduit is disclosed. The clamping apparatus comprises a base portion fastened to the conduit and including a bracket for receiving an adapter. The adapter is attached to a housing and allows the housing to be rotated when the adapter is positioned in an upper portion of the bracket, and prevents the housing from being rotated when the adapter is positioned in a lower portion of the bracket. The housing is configured to enclose the ultrasonic transducer except for a housing opening along the bottom of the housing. The ultrasonic transducer extends through the housing opening and is spring biased against the conduit.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: April 28, 2020
    Assignee: General Electric Company
    Inventor: Kai Fan
  • Publication number: 20200004590
    Abstract: A notification for an application stack is received, where the application stack includes a plurality of resource types. At least one policy associated with the notification is obtained, with the first policy being a policy for scaling a first resource of a first resource type and a second resource of a second resource type of the application stack. A first capacity for the first resource and a second capacity for the second resource is determined based at least in part on the at least one policy. The first resource and the second resource are caused to be scaled according to the first capacity and the second capacity respectively.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 2, 2020
    Inventors: Kai Fan Tang, Ahmed Usman Khalid