Abstract: The present disclosure provides a chemical mechanical polishing device including a retaining ring and a wafer carrier and a polishing method. The retaining ring is configured on a polishing pad and includes an inner sidewall defining an opening and an outer sidewall opposite to the inner sidewall. The wafer carrier is configured on the polishing pad and is capable of placing a wafer disposed thereon into the opening and facing the polishing pad. The retaining ring has a notch at the corner adjacent to the wafer and the polishing pad.

Abstract: An ultra thin package for an electric acoustic sensor chip of a micro electro mechanical system is provided. A substrate has a first substrate surface and a second substrate surface opposite to the first substrate surface. At least one conductor bump is formed on the second substrate surface. An electric acoustic sensor chip having a first chip surface and a second chip surface opposite to the first chip surface is provided. The first chip surface is electrically connected to the conductor bump. The conductor bump is positioned between the second substrate surface and the first chip surface to create a space. The conductor bump is used for transferring a signal from the sensor chip to the substrate. An acoustic opening passing through the substrate is formed.

Abstract: An acoustic transducer comprises a substrate, a membrane configured to move relative to the substrate, a number of supports configured to suspend the membrane over the substrate, a first group of projections extending from the membrane, and a second group of projections extending from the substrate, the second group of projections being interweaved with and movable relative to the first group of projections, wherein each projection of one group of the first group of projections and the second group of projections is composed of a first conductive layer, a second conductive layer and a dielectric layer between the first conductive layer and the second conductive layer, and each projection of the other one group of the first group of projections and the second group of projections is composed of a third conductive layer.

Abstract: An electro-acoustic sensing device including a sensing chip, a carrier chip and a sealing element is provided. The sensing chip is for electro-acoustic transuding and thereby outputting an electrical signal. The carrier chip disposed below the sensing chip has at least one second connecting point, at least one electrical channel and at least one channel connecting point. The second connecting point is electrically contacted with the first connecting point. The second connecting point and the channel connecting point are located at different surfaces of the carrier chip. The electrical channel passes through the carrier chip and electrically connects the second connecting point and the channel connecting point. The electrical signal is transmitted to the channel connecting point via the first and the second connecting points and the electrical channel. The sealing element is disposed between the sensing chip and the carrier chip for air-tight coupling the two chips.

Abstract: A sensor including a carrier, a plurality of conductive bumps, a capacitive sensing element connected to the carrier through the conductive bumps, and a cover is provided. The capacitive sensing element has a membrane, and a channel is formed among the capacitive sensing element, the conductive bumps, and the carrier. The cover is disposed on the carrier for covering the capacitive sensing element. A chamber is formed between the capacitive sensing element and the cover. The chamber and the channel are respectively located at two sides of the membrane.

Abstract: A sensor including a carrier, a plurality of conductive bumps, a capacitive sensing element connected to the carrier through the conductive bumps, and a cover is provided. The capacitive sensing element has a membrane, and a channel is formed among the capacitive sensing element, the conductive bumps, and the carrier. The cover is disposed on the carrier for covering the capacitive sensing element. A chamber is formed between the capacitive sensing element and the cover. The chamber and the channel are respectively located at two sides of the membrane.

Abstract: A sensor including a carrier having two channels, a capacitive sensing element disposed on the carrier, and a cover is provided. The capacitive sensing element has a membrane, and a first chamber is formed between the membrane and the carrier. The cover is disposed on the carrier for covering the capacitive sensing element. A second chamber is formed between the membrane and the cover. The first chamber and the second chamber are located at two sides of the membrane, and the channels are respectively communicated with the first chamber and the second chamber.

Abstract: An ultra thin package for an electric acoustic sensor chip of a micro electro mechanical system is provided. A substrate has a first substrate surface and a second substrate surface opposite to the first substrate surface. At least one conductor bump is formed on the second substrate surface. An electric acoustic sensor chip having a first chip surface and a second chip surface opposite to the first chip surface is provided. The first chip surface is electrically connected to the conductor bump. The conductor bump is positioned between the second substrate surface and the first chip surface to create a space. The conductor bump is used for transferring a signal from the sensor chip to the substrate. An acoustic opening passing through the substrate is formed.

Abstract: A sensor including a carrier having two channels, a capacitive sensing element disposed on the carrier, and a cover is provided. The capacitive sensing element has a membrane, and a first chamber is formed between the membrane and the carrier. The cover is disposed on the carrier for covering the capacitive sensing element. A second chamber is formed between the membrane and the cover. The first chamber and the second chamber are located at two sides of the membrane, and the channels are respectively communicated with the first chamber and the second chamber.

Abstract: An electro-acoustic sensing device including a sensing chip, a carrier chip and a sealing element is provided. The sensing chip is for electro-acoustic transducing and thereby outputting an electrical signal. The carrier chip disposed below the sensing chip has at least one second connecting point, at least one electrical channel and at least one channel connecting point. The second connecting point is electrically contacted with the first connecting point. The second connecting point and the channel connecting point are located at different surfaces of the carrier chip. The electrical channel passes through the carrier chip and electrically connects the second connecting point and the channel connecting point. The electrical signal is transmitted to the channel connecting point via the first and the second connecting points and the electrical channel. The sealing element is disposed between the sensing chip and the carrier chip for air-tight coupling the two chips.

Abstract: An acoustic transducer comprises a substrate, a membrane configured to move relative to the substrate, a number of supports configured to suspend the membrane over the substrate, a first group of projections extending from the membrane, and a second group of projections extending from the substrate, the second group of projections being interweaved with and movable relative to the first group of projections, wherein each projection of one group of the first group of projections and the second group of projections is composed of a first conductive layer, a second conductive layer and a dielectric layer between the first conductive layer and the second conductive layer, and each projection of the other one group of the first group of projections and the second group of projections is composed of a third conductive layer.

Abstract: The specification discloses a structure and method for measuring the etching speed. A test layer is connected with several resistors. Etching the metal layer disconnects in order the resistors from the circuit. The equivalent resistance of the sensing resistor system is measured to obtain the etching speed. In consideration of the errors of the resistors, the invention also provides a structure that utilizes an IC layout technique to put an interdigitized dummy resistor beside the sensing resistors. By taking the ratio of the equivalent resistance of the sensing resistors and the dummy resistor, the invention can compute to obtain the etching speed.

Abstract: A fabrication method for microstructures with high aspect ratios uses a CMOS process to form a desired microstructure on a silicon substrate. The steps of forming a contact plug and a via plug of the process are used to form etching channels in insulation layers, polysilicon layers and metal layers, penetrating to the silicon substrate. An etching process is then performed through the etching channel to form the desired microstructure with high aspect ratio.

Abstract: An apparatus of wafer level package for the micro elements and methods of fabricating the same is disclosed. The apparatus is utilized to provide a lid substrate for bonding the lid substrate to a substrate having several micro elements and therefore form a cavity capable of being operated for the micro elements. The openings of the cavity are used to make the micro elements capable of being contacted with the atmosphere and therefore form an apparatus of wafer level package for the micro elements.

Abstract: A fabrication method for microstructures with high aspect ratios uses a CMOS process to form a desired microstructure on a silicon substrate. The steps of forming a contact plug and a via plug of the process are used to form etching channels in insulation layers, polysilicon layers and metal layers, penetrating to the silicon substrate. An etching process is then performed through the etching channel to form the desired microstructure with high aspect ratio.

Abstract: The specification discloses a structure and method for measuring the etching speed. A test layer is connected with several resistors. Etching the metal layer disconnects in order the resistors from the circuit. The equivalent resistance of the sensing resistor system is measured to obtain the etching speed. In consideration of the errors of the resistors, the invention also provides a structure that utilizes an IC layout technique to put an interdigitized dummy resistor beside the sensing resistors. By taking the ratio of the equivalent resistance of the sensing resistors and the dummy resistor, the invention can compute to obtain the etching speed.

Abstract: The specification discloses a structure and method for measuring the etching speed. A test layer is connected with several resistors. Etching the metal layer disconnects in order the resistors from the circuit. The equivalent resistance of the sensing resistor system is measured to obtain the etching speed. In consideration of the errors of the resistors, the invention also provides a structure that utilizes an IC layout technique to put an interdigitized dummy resistor beside the sensing resistors. By taking the ratio of the equivalent resistance of the sensing resistors and the dummy resistor, the invention can compute to obtain the etching speed.

Abstract: Test structure and method of step coverage for optical waveguide production are disclosed. It combines the steps of producing the optical waveguide and the testing structure by forming the optical waveguide components on the chip and the test structure in the surrounding areas, so the optical waveguide and the test structure have the same upper covering layer. Etching solution is used for the etch testing of the test structure, and the step coverage of the upper covering layer for the optical waveguide is extrapolated by the etching result.

Abstract: The specification discloses a structure and method for measuring the etching speed. A test layer is connected with several resistors. Etching the metal layer disconnects in order the resistors from the circuit. The equivalent resistance of the sensing resistor system is measured to obtain the etching speed. In consideration of the errors of the resistors, the invention also provides a structure that utilizes an IC layout technique to put an interdigitized dummy resistor beside the sensing resistors. By taking the ratio of the equivalent resistance of the sensing resistors and the dummy resistor, the invention can compute to obtain the etching speed.

Abstract: Test structure and method of step coverage for optical waveguide production are disclosed. It combines the steps of producing the optical waveguide and the testing structure by forming the optical waveguide components on the chip and the test structure in the surrounding areas, so the optical waveguide and the test structure have the same upper covering layer. Etching solution is used for the etch testing of the test structure, and the step coverage of the upper covering layer for the optical waveguide is extrapolated by the etching result.