Abstract: A sealing mechanism is provided, including a housing, a groove, and a sealing element. The housing includes a first member and a second member, and the groove is formed between the first and second members. The sealing element is formed in the groove by Low Pressure Molding (LPM) and surrounds at least one of the first and second members.

Abstract: A power connector module is provided, including a housing, an electrical connector unit disposed in a first space of the housing, and a socket unit disposed in a second space of the housing. The glue is received in the first space, and a gate plate is disposed on a diaphragm of the housing to prevent the glue from flowing into the second space.

Abstract: A method of manufacturing a semiconductor device is provided, including: forming a first conductive type lightly doped region in the epitaxial layer; forming a first conductive type heavily doped region and a second conductive type heavily doped region in the epitaxial layer on the first conductive type lightly doped region, in which the neighboring first conductive type heavily doped regions are spaced apart by the second conductive type heavily doped region; disposing the mask on the second conductive type heavily doped region; disposing a spacer on a sidewall of the mask; doping a first conductive type dopant in the first conductive type lightly doped region to form an anti-breakdown region; removing the mask and forming a trench extending into the second conductive type heavily doped region, first conductive type lightly doped region and the epitaxial layer; and removing the spacer.

Abstract: A method according to the present disclosure includes providing a workpiece including a first fin-shaped structure and a second fin-shaped structure over a substrate, depositing a nitride liner over the substrate and sidewalls of the first fin-shaped structure and the second fin-shaped structure, forming an isolation feature over the nitride liner and between the first fin-shaped structure and the second fin-shaped structure, epitaxially growing a cap layer on exposed surfaces of the first fin-shaped structure and the second fin-shaped structure and above the nitride liner, crystalizing the cap layer, and forming a first source/drain feature over a first source/drain region of the first fin-shaped structure and a second source/drain feature over a second source/drain region of the second fin-shaped structure.

Abstract: A method of forming a semiconductor device includes forming an epitaxial layer on a substrate, forming a hard mask layer on the epitaxial layer, forming a JFET region in the epitaxial layer by using the hard mask layer and removing the hard mask layer, forming a staircase-shaped hard mask stack on the JFET region, forming a well region in the epitaxial layer by using the staircase-shaped hard mask stack, in which a bottom of the JFET region is lower than a bottom of the well region and the bottom of the well region is in contact with the JFET region and a drift region of the epitaxial layer simultaneously, forming a source region in the well region, removing the staircase-shaped hard mask stack, and forming a gate structure on the JFET region.

Abstract: A method of manufacturing a semiconductor device includes forming an epitaxial layer on a substrate, forming a hard mask on the epitaxial layer, in which the hard mask includes a first portion and a second portion, with a gap therebetween, performing an oxidation process to form an oxide layer on a surface of the hard mask, forming a source region in the epitaxial layer through the gap of the hard mask, forming a well region in the epitaxial layer using the second portion of the hard mask as a mask, forming a sacrificial layer on the source region and the well region, removing the second portion of the hard mask, forming a JFET region in the epitaxial layer using the sacrificial layer as a mask, forming a dielectric layer on the JFET region, removing the sacrificial layer and forming a gate structure adjacent the dielectric layer.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; patterning the epitaxial layer into a semiconductor fin; depositing a conformal semiconductor capping layer over the semiconductor fin, wherein the conformal semiconductor capping layer has a first portion that is amorphous; performing a thermal treatment such that the first portion of the conformal semiconductor capping layer is converted from amorphous into crystalline; depositing a dielectric material over the conformal semiconductor capping layer; annealing the dielectric material, such that the conformal semiconductor capping layer is converted into a semiconductor-containing oxide layer; recessing the dielectric material and the semiconductor-containing oxide layer to form an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin and the isolation structure.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate, in which the substrate is SiC base. The substrate, from bottom to top, sequentially includes an N-type heavy doping base layer, an N-type light doping layer, a P-well region, and an N-type heavy doping layer. The substrate is etched by using a patterned mask to form a gate trench and a channel region defined by the gate trench. The channel region is shielded by the patterned mask. An ion implant is performed to the gate trench such that a shielding implant layer is formed on the bottom of the gate trench. An oxidation process is performed to the gate trench thereby forming a gate oxide layer. The oxidation rate at the bottom of the gate trench is faster than the oxidation rate at the sidewall of the gate trench. A semiconductor device is also provided.

Abstract: A method includes etching a semiconductor substrate to form a trench and a semiconductor strip. A sidewall of the semiconductor strip is exposed to the trench. The method further includes depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip, filling the trench with a dielectric material, wherein the dielectric material is on a sidewall of the silicon-containing layer, and oxidizing the silicon-containing layer to form a liner. The liner comprises oxidized silicon. The liner and the dielectric material form parts of an isolation region. The isolation region is recessed, so that a portion of the semiconductor strip protrudes higher than a top surface of the isolation region and forms a semiconductor fin.

Abstract: A manufacturing method of an abrasion resistant mesh fabric includes the following steps: a) arranging a gel applying mechanism, the gel applying mechanism having a gel applying roller, and a drive roller and a scraper, which are located by two opposite sides of the gel applying roller respectively and arranged separately from the gel applying roller, polyurethane gel being stored between the scraper and the outer surface of the gel applying roller in a contact manner with the outer surface of the gel applying roller; b) conveying a mesh fabric base material to pass between the gel applying roller and the drive roller in a way that the polyurethane gel clinging to the gel applying roller is applied to one side of the mesh fabric base material; and c) moisture hardening the polyurethane gel applied on the side of the mesh fabric base material at room temperature.

Abstract: A method includes etching a semiconductor substrate to form a trench and a semiconductor strip. A sidewall of the semiconductor strip is exposed to the trench. The method further includes depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip, filling the trench with a dielectric material, wherein the dielectric material is on a sidewall of the silicon-containing layer, and oxidizing the silicon-containing layer to form a liner. The liner comprises oxidized silicon. The liner and the dielectric material form parts of an isolation region. The isolation region is recessed, so that a portion of the semiconductor strip protrudes higher than a top surface of the isolation region and forms a semiconductor fin.

Abstract: A semiconductor device includes a substrate, an epitaxial layer, a well region, a source region, a base region, a first JFET region, a second JFET region, a gate dielectric layer and a gate layer. The epitaxial layer is at a side of the substrate. The well region is in the epitaxial layer. The source region is in the well region. The base region is in the well region and adjacent to the source region. The first JFET region is adjacent to the well region. The second JFET region is in the first JFET region. A doping concentration of the second JFET region is higher than a doping concentration of the first JFET region. The gate dielectric layer is at a side of the epitaxial layer away from the substrate. The gate layer is at a side of the gate dielectric layer away from the epitaxial layer.

Abstract: A sealing mechanism is provided, including a housing, a groove, and a sealing element. The housing includes a first member and a second member, and the groove is formed between the first and second members. The sealing element is formed in the groove by Low Pressure Molding (LPM) and surrounds at least one of the first and second members.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A base region is formed in a substrate. A protective layer is formed on the substrate and covers the base region. First and second sacrificial layers are formed on the substrate and cover the protective layer. A source region, a well region, and a junction field effect transistor (JFET) region are formed in the substrate. When the source region, the well region, and the JFET region are formed in sequence, the source region and the well region are formed by the first sacrificial layer, and the JFET region is formed by the second sacrificial layer. When the JFET region, the well region, and the source region are formed in sequence, the JFET region is formed by the first sacrificial layer, and the well region and the source region are formed by the second sacrificial layer.

Abstract: A method of forming a semiconductor device includes forming a P-type heavily doped region in a substrate. A sacrificial layer is formed on the substrate and covers the P-type heavily doped region. The sacrificial layer is patterned, so that sidewalls of the sacrificial layer are above the substrate inside the P-type heavily doped region. An N-type heavily doped region adjacent to the P-type heavily doped region is formed in the substrate by using the sacrificial layer as mask. A wet etching process is performed to retract the sidewalls of the sacrificial layer to the substrate inside the N-type heavily doped region. A P-type lightly doped region is formed in the substrate by using the sacrificial layer as mask. The P-type lightly doped region is adjacent to the N-type heavily doped region, and is in contact with bottoms of the P-type heavily doped region and the N-type heavily doped region.

Abstract: In an embodiment, a method of forming a semiconductor device includes: forming a first oxide layer over a semiconductor fin structure; performing a first nitridation process to convert the first oxide layer to an oxynitride layer; depositing a silicon-containing layer over the oxynitride layer; performing a first anneal on the silicon-containing layer, wherein after performing the first anneal, the oxynitride layer has a higher nitrogen atomic concentration at an interface with the semiconductor fin structure than in a bulk region of the oxynitride layer; and forming a dummy gate structure over the silicon-containing layer.

Abstract: A method includes forming a semiconductor fin protruding over a substrate; forming an isolation structure over the substrate; depositing a first metal oxide layer over the isolation structure; depositing a first oxide layer over the first metal oxide layer; depositing a second metal oxide layer over the first oxide layer, in which the first metal oxide layer and the second metal oxide layer comprise amorphous structures; performing a chemical mechanism polishing (CMP) process to the first metal oxide layer, the first oxide layer, and the second metal oxide layer; after the CMP process is completed, performing an annealing process such that the first metal oxide layer and the second metal oxide layer are transferred from the amorphous structures into crystalline structures; forming a gate structure over the semiconductor fin; and forming source/drain structures over the substrate and on opposite sides of the gate structure.

Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.

Abstract: A power connector module is provided, including a housing, an electrical connector unit disposed in a first space of the housing, and a socket unit disposed in a second space of the housing. The glue is received in the first space, and a gate plate is disposed on a diaphragm of the housing to prevent the glue from flowing into the second space.