Patents by Inventor Kai-Hung Alex See
Kai-Hung Alex See has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10784332Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower conductor element overlying a substrate, and forming a magnetic stack layer overlying the lower conductor element. A waste portion of the magnetic stack layer is removed with a wet etchant to produce a magnetic core. The wet etchant includes hydrofluoric acid, a second acid different than the hydrofluoric acid, an oxidizer, and a solvent.Type: GrantFiled: March 22, 2018Date of Patent: September 22, 2020Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Liang Li, Yun Ling Tan, Kai Hung Alex See, Lulu Peng, Donald Ray Disney
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Patent number: 10483121Abstract: A low-k dielectric layer, such as SiCOH, with high and stable chemical mechanical polishing (CMP) removal rate (RR) is disclosed. The polishing rate enhancer (PRE) is disposed on the low-k dielectric layer. The PRE increases the CMP RR during CMP. Furthermore, the PRE stabilizes the increases CMP RR. This is particularly useful, for example, for memory applications in which the storage unit is formed in a low-k back-end-of-line (BEOL) dielectric layer. For example, the topography created can be quickly planarized by CMP while producing a uniform polished surface of the low-k dielectric layer due to the shortened processing time.Type: GrantFiled: May 31, 2018Date of Patent: November 19, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Lei Wang, Chim Seng Seet, Kai Hung Alex See
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Patent number: 10475495Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a first free layer that is magnetic, a second free layer that is magnetic, and an insertion layer positioned between the first and second free layers. The insertion layer is non-magnetic, and the insertion layer includes terbium.Type: GrantFiled: February 14, 2018Date of Patent: November 12, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wai Cheung Law, Taiebeh Tahmasebi, Chim Seng Seet, Kai Hung Alex See, Gerard Joseph Lim, Wen Siang Lew
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Patent number: 10468171Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a seed layer, first and second pinned layers, and a coupling layer. The seed layer includes holmium. The first pinned layer overlies the seed layer, where the first pinned layer is magnetic, and the non-magnetic coupling layer overlies the first pinned layer. The second pinned layer overlies the coupling layer, where the second pinned layer is also magnetic.Type: GrantFiled: June 27, 2018Date of Patent: November 5, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wai Cheung Law, Taiebeh Tahmasebi, Dimitri Houssameddine, Michael Nicolas Albert Tran, Chim Seng Seet, Kai Hung Alex See, Wen Siang Lew
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Publication number: 20190296100Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower conductor element overlying a substrate, and forming a magnetic stack layer overlying the lower conductor element. A waste portion of the magnetic stack layer is removed with a wet etchant to produce a magnetic core. The wet etchant includes hydrofluoric acid, a second acid different than the hydrofluoric acid, an oxidizer, and a solvent.Type: ApplicationFiled: March 22, 2018Publication date: September 26, 2019Inventors: Liang Li, Yun Ling Tan, Kai Hung Alex See, Lulu Peng, Donald Ray Disney
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Publication number: 20190252600Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a first free layer that is magnetic, a second free layer that is magnetic, and an insertion layer positioned between the first and second free layers. The insertion layer is non-magnetic, and the insertion layer includes terbium.Type: ApplicationFiled: February 14, 2018Publication date: August 15, 2019Inventors: Wai Cheung Law, Taiebeh Tahmasebi, Chim Seng Seet, Kai Hung Alex See, Gerard Joseph Lim, Wen Siang Lew
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Publication number: 20180286694Abstract: A low-k dielectric layer, such as SiCOH, with high and stable chemical mechanical polishing (CMP) removal rate (RR) is disclosed. The polishing rate enhancer (PRE) is disposed on the low-k dielectric layer. The PRE increases the CMP RR during CMP. Furthermore, the PRE stabilizes the increases CMP RR. This is particularly useful, for example, for memory applications in which the storage unit is formed in a low-k back-end-of-line (BEOL) dielectric layer. For example, the topography created can be quickly planarized by CMP while producing a uniform polished surface of the low-k dielectric layer due to the shortened processing time.Type: ApplicationFiled: May 31, 2018Publication date: October 4, 2018Inventors: Lei WANG, Chim Seng SEET, Kai Hung Alex SEE
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Patent number: 10008387Abstract: A low-k dielectric layer, such as SiCOH, with high and stable chemical mechanical polishing (CMP) removal rate (RR) is disclosed. The polishing rate enhancer (PRE) is disposed on the low-k dielectric layer. The PRE increases the CMP RR during CMP. Furthermore, the PRE stabilizes the increases CMP RR. This is particularly useful, for example, for memory applications in which the storage unit is formed in a low-k back-end-of-line (BEOL) dielectric layer. For example, the topography created can be quickly planarized by CMP while producing a uniform polished surface of the low-k dielectric layer due to the shortened processing time.Type: GrantFiled: February 15, 2017Date of Patent: June 26, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Lei Wang, Chim Seng Seet, Kai Hung Alex See
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Patent number: 9997562Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a substrate comprising a circuit component formed on a substrate surface. Back-end-of-line (BEOL) processing is performed to form a plurality of inter-level dielectric (ILD) layers over the substrate. A storage unit in the memory region of the via level of an ILD level. A cell dielectric layer is formed over the storage unit. The cell dielectric layer comprises a step structure created by an elevated topography of the memory region relative to the non-memory region of the via level. The elevated topography is defined by the storage unit. Chemical mechanical polishing (CMP) process is performed on the cell dielectric layer to remove the step structure of the cell dielectric layer and form a planar cell dielectric top surface extending uniformly across the memory region and the non-memory region of the via level.Type: GrantFiled: March 14, 2017Date of Patent: June 12, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Lei Wang, Benfu Lin, Chim Seng Seet, Kai Hung Alex See
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Patent number: 7553678Abstract: A method for detecting semiconductor-manufacturing conditions includes providing a photomask with a plurality of pattern areas each having a plurality of test lines with different pitches, exposing a plurality of wafer with the photomask in different manufacturing conditions, measuring the critical dimensions of the plurality of pattern areas, generating a library of relationships between the pitches and the critical dimension of the pattern areas, exposing a test wafer in an unknown manufacturing condition, finding out a relationships between the pitches and the critical dimension of the pattern areas of the test wafer, searching for a most similar relationship in the library, and detecting a set of manufacturing parameters used to expose the test wafer.Type: GrantFiled: March 17, 2006Date of Patent: June 30, 2009Assignee: United Microelectronics Corp.Inventors: Wen-Zhan Zhou, Jin Yu, Kai-Hung Alex See
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Patent number: 7527900Abstract: An OPC method includes providing a primary mask having a primary pattern, forming an assist mask having a correction pattern substantially complementary to the primary pattern, and forming a reticle by overlapping the primary mask and the assist mask. The light transmittance of the correction pattern is adjustable so as to equalize the light intensity distribution of the primary mask.Type: GrantFiled: November 10, 2005Date of Patent: May 5, 2009Assignee: United Microelectronics Corp.Inventors: Wen-Zhan Zhou, Jin Yu, Kai-Hung Alex See
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Publication number: 20070220458Abstract: A method for detecting semiconductor-manufacturing conditions includes providing a photomask with a plurality of pattern areas each having a plurality of test lines with different pitches, exposing a plurality of wafer with the photomask in different manufacturing conditions, measuring the critical dimensions of the plurality of pattern areas, generating a library of relationships between the pitches and the critical dimension of the pattern areas, exposing a test wafer in an unknown manufacturing condition, finding out a relationships between the pitches and the critical dimension of the pattern areas of the test wafer, searching for a most similar relationship in the library, and detecting a set of manufacturing parameters used to expose the test wafer.Type: ApplicationFiled: March 17, 2006Publication date: September 20, 2007Inventors: Wen-Zhan Zhou, Jin Yu, Kai-Hung Alex See
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Publication number: 20070167110Abstract: A multi-zone carrier head includes a housing; a retaining ring secured to a lower edge of the housing; a backing plate having a plurality of non-concentric pressure zones defined by a plurality of isolated apertures on the backing plate; wherein the backing plate has a wafer side and a non-wafer side, the wafer side facing a backside of a wafer during a CMP operation; and a plurality of pneumatic bladder for independently controlling pressure exerted in the respective non-concentric pressure zones on the backside of the wafer during the CMP operation.Type: ApplicationFiled: January 16, 2006Publication date: July 19, 2007Inventors: Yu-Hsiang Tseng, Kai-Hung Alex See, Mei-Sheng Zhou, Jin Yu, Zheng Zou, Wen-Zhan Zhou
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Publication number: 20070105023Abstract: An OPC method includes providing a primary mask having a primary pattern, forming an assist mask having a correction pattern substantially complementary to the primary pattern, and forming a reticle by overlapping the primary mask and the assist mask. The light transmittance of the correction pattern is adjustable so as to equalize the light intensity distribution of the primary mask.Type: ApplicationFiled: November 10, 2005Publication date: May 10, 2007Inventors: Wen-Zhan Zhou, Jin Yu, Kai-Hung Alex See
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Publication number: 20070066047Abstract: A method for forming an opening on a material layer is provided. First, a dielectric layer is formed on the material layer. Then, a metallic hard mask layer and a cap layer are sequentially formed on the dielectric layer. Thereafter, a patterned photoresist layer is formed on the cap layer. The patterned photoresist layer exposes a portion of the surface of the cap layer. After that, a first etching operation is carried out using the patterned photoresist layer as a mask to remove a portion of the cap layer and the metallic hard mask layer until the surface of the dielectric layer is exposed. Then, the photoresist layer is removed. A second etching operation is carried out using the cap layer and the metallic hard mask layer as a mask to remove a portion of the dielectric layer and form an opening.Type: ApplicationFiled: September 18, 2005Publication date: March 22, 2007Inventors: Jianhui Ye, Kai Hung Alex See, Tien-Cheng Lan, Meisheng Zhou