Abstract: The present disclosure provides a method of forming a capacitor. The method includes the following operations. A metal oxide insulating layer is formed on a first conductive layer with a first temperature, in which the first temperature is lower than a crystallization temperature of the metal oxide insulating layer. A second conductive layer is formed on the metal oxide insulating layer with a second temperature. An insulating layer is formed on the second conductive layer with a third temperature to crystallize the metal oxide insulating layer to form a crystallized metal oxide insulating layer, in which the second temperature is between the first temperature and the third temperature.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: forming a first semiconductor layer on an inner surface of a trench of a substrate; forming a second semiconductor layer on the first semiconductor layer on the inner surface of the trench of the substrate; forming another first semiconductor layer on the second semiconductor layer on the inner surface of the trench of the substrate; forming another second semiconductor layer on the another first semiconductor layer on the inner surface of the trench of the substrate, in which the second semiconductor layer is sandwiched between the first semiconductor layer and the another first semiconductor layer, and the another first semiconductor layer is sandwiched between the second semiconductor layer and the another second semiconductor layer; and forming a third semiconductor layer on the another second semiconductor layer.

Abstract: The present application provides a storage capacitor with multiple dielectrics. The storage capacitor includes a lower electrode, an upper electrode, a first dielectric layer, a second dielectric layer and a third dielectric layer. The first dielectric layer covers the lower electrode, the second dielectric layer is disposed on the first dielectric layer, and the third dielectric layer is disposed on the second dielectric layer. The upper electrode is disposed on the third dielectric layer.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: depositing a first semiconductor layer on an inner surface of a trench of a substrate; depositing a second semiconductor layer on the first semiconductor layer on the inner surface of the trench of the substrate, in which a dopant concentration of the first semiconductor layer is less than a dopant concentration of the second semiconductor layer; and depositing a third semiconductor layer on the second semiconductor layer to fill the trench of the substrate, in which a dopant concentration of the third semiconductor layer is less than the dopant concentration of the second semiconductor layer.

Abstract: A method of forming a capacitor structure includes following operations. A first electrode is formed. A hafnium-zirconium oxide (HZO) layer is formed over the first electrode under a first temperature. An interface dielectric layer is formed over the HZO layer under a second temperature greater than the first temperature. A second electrode is formed over the interface dielectric layer. The HZO layer and the interface dielectric layer are annealed.

Abstract: The present disclosure provides a method for preparing a memory device. The method includes forming a doped region in a semiconductor substrate, and forming a word line across the doped region such that a first source/drain region and a second source/drain region are formed in the doped region and at opposite sides of the word line. The method also includes forming a bit line over and electrically connected to the first source/drain region, and forming a capacitor over and electrically connected to the second source/drain region. The formation of the capacitor includes forming a bottom electrode, forming a capacitor dielectric structure over the bottom electrode, and forming a top electrode over the capacitor dielectric structure.

Abstract: A method of forming a capacitor structure includes following operations. A first electrode is formed. A hafnium-zirconium oxide (HZO) layer is formed over the first electrode under a first temperature. An interface dielectric layer is formed over the HZO layer under a second temperature greater than the first temperature. A second electrode is formed over the interface dielectric layer. The HZO layer and the interface dielectric layer are annealed.

Abstract: A memory device includes a semiconductor substrate having an active region, and a word line extending across the active region. The memory device also includes a first source/drain region and a second source/drain region disposed in the active region and at opposite sides of the word line, a bit line disposed over and electrically connected to the first source/drain region, and a capacitor disposed over and electrically connected to the second source/drain region. The capacitor includes a bottom electrode, a top electrode, and a capacitor dielectric structure disposed between them. The capacitor dielectric structure includes a first metal oxide layer, a second metal oxide layer disposed over the first metal oxide layer, and a third metal oxide layer disposed over the second metal oxide layer. The first, the second and the third metal oxide layer include materials that are different from each other.

Abstract: The present application provides a method of fabricating a storage capacitor. The method includes steps of forming a lower electrode; depositing a first dielectric layer covering the lower electrode; depositing a second dielectric layer on the first dielectric layer; depositing a third dielectric layer on the second dielectric layer; and forming an upper electrode on the third dielectric layer.

Abstract: The present application provides a storage capacitor with multiple dielectrics. The storage capacitor includes a lower electrode, an upper electrode, a first dielectric layer, a second dielectric layer and a third dielectric layer. The first dielectric layer covers the lower electrode, the second dielectric layer is disposed on the first dielectric layer, and the third dielectric layer is disposed on the second dielectric layer. The upper electrode is disposed on the third dielectric layer.

Abstract: A method of forming a capacitor structure includes following operations. A first electrode is formed. A hafnium-zirconium oxide (HZO) layer is formed over the first electrode under a first temperature. An interface dielectric layer is formed over the HZO layer under a second temperature greater than the first temperature. A second electrode is formed over the interface dielectric layer. The HZO layer and the interface dielectric layer are annealed.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: depositing a first semiconductor layer on an inner surface of a trench of a substrate; depositing a second semiconductor layer on the first semiconductor layer on the inner surface of the trench of the substrate, in which a dopant concentration of the first semiconductor layer is less than a dopant concentration of the second semiconductor layer; and depositing a third semiconductor layer on the second semiconductor layer to fill the trench of the substrate, in which a dopant concentration of the third semiconductor layer is less than the dopant concentration of the second semiconductor layer.

Abstract: A method of forming a capacitor structure includes following operations. A first electrode is formed. A hafnium-zirconium oxide (HZO) layer is formed over the first electrode under a first temperature. An interface dielectric layer is formed over the HZO layer under a second temperature greater than the first temperature. A second electrode is formed over the interface dielectric layer. The HZO layer and the interface dielectric layer are annealed.

Abstract: An identification method of an integrated circuit chip of the present invention includes identifying a surface structure or an internal structure of an integrated circuit chip, generating a structural information set according to the surface structure or internal structure, converting the structural information set into an identification information set. The identification information set generated by the above-mentioned identification method can be stored in a digital file, and a chip manufacturer requires no visible information printed on an outer surface of the integrated circuit chip such that factory information of the integrated circuit chip can be concealed.

Abstract: An energy saving air conditioning system is disclosed which provides different air conditioning modes, including a closed-loop mode, an open-loop mode, and a partial-loop mode, for controlling the environment in a high-density apparatus room. The energy saving air conditioning system uses a cloud operating center to monitor the temperature and the moisture inside and outside the high-density apparatus room. The cloud operating system dynamically selects the air conditioning mode in such a manner that energy can be saved and the environment in the high-density apparatus room can be optimally managed.

Abstract: An energy saving air conditioning system is disclosed which provides different air conditioning modes, including a closed-loop mode, an open-loop mode, and a partial-loop mode, for controlling the environment in a high-density apparatus room. The energy saving air conditioning system uses a cloud operating center to monitor the temperature and the moisture inside and outside the high-density apparatus room. The cloud operating system dynamically selects the air conditioning mode in such a manner that energy can be saved and the environment in the high-density apparatus room can be optimally to managed.

Abstract: A cooling apparatus for server rack is disclosed, which is disposed above at least one server rack. The cooling apparatus for server rack includes a fan module disposed at a back end above the least one server rack, a heat exchanger module disposed at a front end above the least one server rack, and an air guide connecting the fan module and the heat exchanger module. A hot air exhausted from the back end of the least one server rack is extracted by the fan module and is sent to the heat exchanger module through the air guide, and the hot air is cooled by the heat exchanger module, and a cool air is exhausted from the front end of the least one server rack.

Abstract: A cooling apparatus for server rack is disclosed, which is disposed above at least one server rack. The cooling apparatus for server rack includes a fan module disposed at a back end above the least one server rack, a heat exchanger module disposed at a front end above the least one server rack, and an air guide connecting the fan module and the heat exchanger module. A hot air exhausted from the back end of the least one server rack is extracted by the fan module and is sent to the heat exchanger module through the air guide, and the hot air is cooled by the heat exchanger module, and a cool air is exhausted from the front end of the least one server rack.

Abstract: A commutate silencer of a computer system is described. The commutate silencer of the computer system is installed at the back end of the computer system, and comprises a shield device, a commutate device and at least one partition. The shield device comprises a first shield and a second shield, in which the first shield comprises an opening, the first shield and the second shield construct a first cavity, and the first cavity includes a plurality of outlets. The commutate device comprises a frame and a plurality of commutate diversion plates, in which the frame construct a second cavity, the diversion plates traverse the second cavity, the second cavity has an inlet and a ventilated opening, and the ventilated opening is connected to the opening of the first shield.

Abstract: A commutate silencer of a computer system is described. The commutate silencer of the computer system is installed at the back end of the computer system, and comprises a shield device, a commutate device and at least one partition. The shield device comprises a first shield and a second shield, in which the first shield comprises an opening, the first shield and the second shield construct a first cavity, and the first cavity includes a plurality of outlets. The commutate device comprises a frame and a plurality of commutate diversion plates, in which the frame construct a second cavity, the diversion plates traverse the second cavity, the second cavity has an inlet and a ventilated opening, and the ventilated opening is connected to the opening of the first shield.