Abstract: A behavior recognition device for recognizing behaviors of a semiconductor manufacturing apparatus includes a storage device and a control unit. The storage device is configured to store log data of the semiconductor manufacturing apparatus. The control unit is cooperatively connected to the storage device, and configured to build a transition state model based on the log data to analyze behaviors related to wafer transfer sequences and manufacturing operations of the semiconductor manufacturing apparatus.

Abstract: A method for producing vapor-grown carbon fibers (VGCF) having a three-dimensional linkage structure is disclosed. The method includes directly delivering heterogeneous catalysts dissolved in a liquid hydrocarbon raw material into a reaction chamber so as to continuously grow vapor-grown carbon fibers having a three-dimensional linkage structure without additional treatment. The method adopts a fluidized bed method, wherein a raw material solution consisting of a hydrocarbon compound, ferrocene (Fe(C5H5)2), thiophene and an organometalic (non-iron) compound is vaporized by preheat. Thereafter, the raw material gas and hydrogen gas are injected into a tubular reactor and pyrolized to produce vapor-grown carbon fibers with 3-D linkage structure.

Abstract: A reaction apparatus for producing vapor-grown carbon fibers (VGCF) and a continuous production system for producing VGCF are disclosed. The VGCF reaction apparatus is featured in installing a plurality of holes on the upper portion of inner tubes; and filling thermally conductive material in the areas between the inner tubes and the outer tube. The continuous production system includes the reaction apparatus, a product collection system and a carrier-gas collecting system, wherein carbon fibers produced by the reaction apparatus fall into the product collection system, and in the product collection system, a collection bin full-loaded with carbon fibers is pushed out and an empty bin is pushed into the collection chamber under PLC control as well as atmosphere replacement with inert gas, thereby continuously producing VGCF.

Abstract: This invention provides a method for fabricating golf club head parts of high strength. At first, vapor grown carbon fibers (VGCF) with 3-D linkage structure is directly grown through a fluidized bed process. Then the VGCF in weight of less than 50 wt % is compounded with 50 wt %˜99 wt % thermoplastic resin or thermosetting resin so as to make a composite material. Thereafter, the composite material is injection-molded or compression-molded to form the golf club head parts with outstanding strength and modulus, light weight, low linear expansion coefficient and high vibration absorption.

Abstract: A reaction apparatus for producing vapor-grown carbon fibers (VGCF) and a continuous production system for producing VGCF are disclosed. The VGCF reaction apparatus is featured in installing a plurality of holes on the upper portion of inner tubes; and filling thermally conductive material in the areas between the inner tubes and the outer tube. The continuous production system includes the reaction apparatus, a product collection system and a carrier-gas collecting system, wherein carbon fibers produced by the reaction apparatus fall into the product collection system, and in the product collection system, a collection bin full-loaded with carbon fibers is pushed out and an empty bin is pushed into the collection chamber under PLC control as well as atmosphere replacement with inert gas, thereby continuously producing VGCF.

Abstract: A method for testing latch-up phenomenon of a chip is provided. The chip is tested on a test platform, the test platform storing a test program of the chip for testing the chip. The method includes (a) obtaining the test program of the chip tested on the test platform, (b) obtaining pin data of the chip by the test program of the chip, (c) setting up an input pin of the chip with an initial value, and (d) providing a test current to the pin of the chip, and then measuring the current between a power end and a ground end of the chip to see if it exceeds a first predetermined value.

Abstract: A method for producing vapor-grown carbon fibers (VGCF) having a three-dimensional linkage structure is disclosed. The method includes directly delivering heterogeneous catalysts dissolved in a liquid hydrocarbon raw material into a reaction chamber so as to continuously grow vapor-grown carbon fibers having a three-dimensional linkage structure without additional treatment. The method adopts a fluidized bed method, wherein a raw material solution consisting of a hydrocarbon compound, ferrocene (Fe(C5H5)2), thiophene and an organometalic (non-iron) compound is vaporized by preheat. Thereafter, the raw material gas and hydrogen gas are injected into a tubular reactor and pyrolized to produce vapor-grown carbon fibers with 3-D linkage structure.

Abstract: A method for testing latch-up phenomenon of a chip is provided. The chip is tested on a test platform, the test platform storing a test program of the chip for testing the chip. The method includes (a) obtaining the test program of the chip tested on the test platform, (b) obtaining pin data of the chip by the test program of the chip, (c) setting up an input pin of the chip with an initial value, and (d) providing a test current to the pin of the chip, and then measuring the current between a power end and a ground end of the chip to see if it exceeds a first predetermined value.

Abstract: A method for reducing a gate length bias is disclosed. The method utilizes an additional blanket ion implantation process to adjust the etching property of the undoped conductive layer. According to the present invention, a polysilicon layer is used to form NMOS and PMOS gate electrodes so that the gate length bias between the NMOS gate electrodes and the PMOS gate electrodes can be effectively reduced.

Abstract: A method for reducing a gate length bias is disclosed. The method utilizes an additional blanket ion implantation process to adjust the etching property of the undoped conductive layer such as a polysilicon layer used to form NMOS and PMOS gate electrodes so that the gate length bias between the NMOS gate electrodes and the PMOS gate electrodes can be effectively reduced.

Abstract: A semiconductor wafer includes a silicon substrate, an active area positioned on the silicon substrate, and a field oxide layer positioned on the surface of the silicon substrate surrounding the active area. The present invention forms a doped area in the silicon substrate and within the active area and then deposits a dielectric layer on the surface of the semiconductor wafer. A dry etching process is performed to remove the dielectric layer. The top power of the dry etching process ranges between three hundred and five hundred watts to prevent damage to the silicon substrate near the field oxide layer and within the active area by the dry etching process, and to reduce the leakage current of the doped area. Additionally, the present invention also uses a wet etching process to remove the dielectric layer, which prevents an anisotropic physical impact on the silicon substrate near the field oxide layer to reduce the leakage current of the doped area.