Patents by Inventor Kaijin Huang

Kaijin Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12211554
    Abstract: A memory device, a system, and a method for operating the memory device are provided. The memory device includes a first memory string and a peripheral circuit. The first memory string includes a first drain, a first drain select gate (DSG) transistor, a first drain dummy transistor between the first drain and the first DSG transistor, and a plurality of first memory cells. A first drain dummy line is coupled to the first drain dummy transistor, and a first DSG line is coupled to the first DSG transistor. The peripheral circuit is configured to, in a program operation, apply a first DSG voltage to the first DSG line and apply a first drain dummy line voltage to the first drain dummy line to turn on the first drain dummy transistor. The first drain dummy line voltage is greater than the first DSG voltage.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: January 28, 2025
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Kaijin Huang, Jin Lyu, Gang Liu
  • Publication number: 20240395331
    Abstract: In a method for erasing a memory device including memory cells, a first erase operation is performed on a selected memory cell of the memory cells. A first erase verifying operation is performed on the selected memory cell. A second erase verifying operation is performed on the selected memory cell. A second erase operation is performed on the selected memory cell based on results of the first erase verifying operation and the second erase verifying operation.
    Type: Application
    Filed: August 8, 2024
    Publication date: November 28, 2024
    Inventor: Kaijin HUANG
  • Patent number: 12142328
    Abstract: The present disclosure provides a method of erase and erase verification for a memory device. The method includes applying a first erase voltage to erase memory cells of the memory device. The first erase voltage is incrementally increased by a first erase step voltage until the memory cells pass an initial erase verification. The method also includes determining whether the memory cells pass or fail sub-erase verifications by applying sub-erase verification voltages. The method further includes applying a second erase voltage to erase the memory cells after the sub-erase verifications. The second erase voltage is increased from the first erase voltage by a second erase step voltage, which is smaller than the first erase step voltage and is determined according to whether the memory cells pass or fail the sub-erase verifications.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: November 12, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Kaijin Huang
  • Patent number: 12094538
    Abstract: In a method for erasing a memory device including memory cells, a first erase operation is performed on a selected memory cell of the memory cells based on a first erase voltage. A first verifying operation is performed on the selected memory cell based on a first erase verify voltage. A second verifying operation is subsequently performed on the selected memory cell based on a second verify voltage after the selected memory cell passes the first verifying operation. Further, a second erase operation is performed on the selected memory cell based on a second erase voltage after the selected memory cell fails the second verifying operation.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: September 17, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Kaijin Huang
  • Publication number: 20240112742
    Abstract: The present disclosure provides a method of erase and erase verification for a memory device. The method includes applying a first erase voltage to erase memory cells of the memory device. The first erase voltage is incrementally increased by a first erase step voltage until the memory cells pass an initial erase verification. The method also includes determining whether the memory cells pass or fail sub-erase verifications by applying sub-erase verification voltages. The method further includes applying a second erase voltage to erase the memory cells after the sub-erase verifications. The second erase voltage is increased from the first erase voltage by a second erase step voltage, which is smaller than the first erase step voltage and is determined according to whether the memory cells pass or fail the sub-erase verifications.
    Type: Application
    Filed: September 22, 2022
    Publication date: April 4, 2024
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventor: Kaijin HUANG
  • Publication number: 20230035225
    Abstract: A memory device, a system, and a method for operating the memory device are provided. The memory device includes a first memory string and a peripheral circuit. The first memory string includes a first drain, a first drain select gate (DSG) transistor, a first drain dummy transistor between the first drain and the first DSG transistor, and a plurality of first memory cells. A first drain dummy line is coupled to the first drain dummy transistor, and a first DSG line is coupled to the first DSG transistor. The peripheral circuit is configured to, in a program operation, apply a first DSG voltage to the first DSG line and apply a first drain dummy line voltage to the first drain dummy line to turn on the first drain dummy transistor.
    Type: Application
    Filed: October 17, 2022
    Publication date: February 2, 2023
    Inventors: Kaijin Huang, Jin Lyu, Gang Liu
  • Patent number: 11508441
    Abstract: In certain aspects, a memory device includes a first memory string including a first drain, a first drain select gate (DSG) transistor, first memory cells, and a first drain dummy transistor between the first drain and the first DSG transistor. The memory device also includes a first bit line coupled to the first drain, a first drain dummy line coupled to the first drain dummy transistor, a first DSG line coupled to the first DSG transistor, word lines respectively coupled to the first memory cells, and a peripheral circuit configured to perform a program operation on a target memory cell of the first memory cells coupled to a selected word line of the word lines.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: November 22, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Kaijin Huang, Jin Lyu, Gang Liu
  • Publication number: 20220223210
    Abstract: In a method for erasing a memory device including memory cells, a first erase operation is performed on a selected memory cell of the memory cells based on a first erase voltage. A first verifying operation is performed on the selected memory cell based on a first erase verify voltage. A second verifying operation is subsequently performed on the selected memory cell based on a second verify voltage after the selected memory cell passes the first verifying operation. Further, a second erase operation is performed on the selected memory cell based on a second erase voltage after the selected memory cell fails the second verifying operation.
    Type: Application
    Filed: March 29, 2021
    Publication date: July 14, 2022
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventor: Kaijin HUANG
  • Publication number: 20210295922
    Abstract: In certain aspects, a memory device includes a first memory string including a first drain, a first drain select gate (DSG) transistor, first memory cells, and a first drain dummy transistor between the first drain and the first DSG transistor. The memory device also includes a first bit line coupled to the first drain, a first drain dummy line coupled to the first drain dummy transistor, a first DSG line coupled to the first DSG transistor, word lines respectively coupled to the first memory cells, and a peripheral circuit configured to perform a program operation on a target memory cell of the first memory cells coupled to a selected word line of the word lines.
    Type: Application
    Filed: May 4, 2021
    Publication date: September 23, 2021
    Inventors: Kaijin Huang, Jin Lyu, Gang Liu
  • Publication number: 20140112338
    Abstract: The present invention provides a multi-core processor and a method for multiplexing a network management port thereof, and relates to the field of processor technologies. The multi-core processor includes a network management port, an initializing unit, and N control planes. The multi-core processor and the method for multiplexing the network management port thereof according to the present invention, by enabling the network management port packet reception interrupt for the management control plane, implement multiplexing of the network management port between multiple control planes.
    Type: Application
    Filed: October 2, 2013
    Publication date: April 24, 2014
    Inventor: Kaijin Huang