Patents by Inventor Kai Keung Chan
Kai Keung Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11438199Abstract: A transmitter device having a calibrator circuit is disclosed. The calibrator circuit performs duty cycle calibration and phase calibration on a plurality of clock signals of the transmitter device. In one embodiment, the phase calibration is performed based on a comparison of the clock signals to a reference clock signal from the plurality of clock signals. In another embodiment, the calibrator circuit uses fixed patterns of data signals to perform phase calibration on the plurality of clock signals.Type: GrantFiled: May 18, 2021Date of Patent: September 6, 2022Assignee: eTopus Technology Inc.Inventors: Danfeng Xu, Xiaolong Liu, Hon Man Yau, Paul K. Lai, Kai Keung Chan
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Patent number: 11349689Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.Type: GrantFiled: May 1, 2020Date of Patent: May 31, 2022Assignee: eTopus Technology Inc.Inventors: Kai Keung Chan, Danfeng Xu, Yu Kou
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Publication number: 20200259684Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.Type: ApplicationFiled: May 1, 2020Publication date: August 13, 2020Inventors: Kai Keung Chan, Danfeng Xu, Yu Kou
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Patent number: 10680857Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.Type: GrantFiled: March 5, 2019Date of Patent: June 9, 2020Assignee: eTopus Technology Inc.Inventors: Kai Keung Chan, Danfeng Xu, Yu Kou
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Publication number: 20190207787Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.Type: ApplicationFiled: March 5, 2019Publication date: July 4, 2019Inventors: Kai Keung Chan, Danfeng Xu, Yu Kou
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Patent number: 10270627Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.Type: GrantFiled: March 14, 2016Date of Patent: April 23, 2019Assignee: eTopus Technology Inc.Inventors: Kai Keung Chan, Danfeng Xu, Yu Kou
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Publication number: 20180062654Abstract: A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.Type: ApplicationFiled: February 2, 2015Publication date: March 1, 2018Applicant: Agate Logic Inc.Inventors: Kai Keung Chan, David Tsang, Shian-Jiun Fu, Chao-Chiang Chen
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Patent number: 9742422Abstract: A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.Type: GrantFiled: June 15, 2016Date of Patent: August 22, 2017Assignee: eTopus Technology Inc.Inventors: Danfeng Xu, Kai Keung Chan, Yu Kou
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Patent number: 9705531Abstract: A multi-mode viterbi decoder supporting different decoding modes. The viterbi decoder comprises circuitry to output one or more data symbol values. The circuitry sets the one or more data symbol values to a first quantity of unit intervals in a first decoding mode (e.g. PAM-4). The circuitry sets the one or more data symbol values to a second quantity of unit intervals in a second decoding mode (e.g. NRZ). The second quantity of unit intervals is greater than the first quantity of unit intervals. A branch metric circuit is adapted to, in the first decoding mode, generate a set of viterbi branch metrics based on the data symbol values for the first quantity of unit intervals. The branch metric circuit is adapted to, in the second decoding mode, generate the set of viterbi branch metrics based on the data symbol values for the second quantity of unit intervals.Type: GrantFiled: February 18, 2015Date of Patent: July 11, 2017Assignee: eTopus Technology Inc.Inventors: Kai Keung Chan, Yu Kou, Tze Yin Cheung, Danfeng Xu
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Publication number: 20160301420Abstract: A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.Type: ApplicationFiled: June 15, 2016Publication date: October 13, 2016Inventors: Danfeng Xu, Kai Keung Chan, Yu Kou
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Publication number: 20160241274Abstract: A multi-mode viterbi decoder supporting different decoding modes. The viterbi decoder comprises circuitry to output one or more data symbol values. The circuitry sets the one or more data symbol values to a first quantity of unit intervals in a first decoding mode (e.g. PAM-4). The circuitry sets the one or more data symbol values to a second quantity of unit intervals in a second decoding mode (e.g. NRZ). The second quantity of unit intervals is greater than the first quantity of unit intervals. A branch metric circuit is adapted to, in the first decoding mode, generate a set of viterbi branch metrics based on the data symbol values for the first quantity of unit intervals. The branch metric circuit is adapted to, in the second decoding mode, generate the set of viterbi branch metrics based on the data symbol values for the second quantity of unit intervals.Type: ApplicationFiled: February 18, 2015Publication date: August 18, 2016Inventors: Kai Keung Chan, Yu Kou, Tze Yin Cheung, Danfeng Xu
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Publication number: 20160226491Abstract: A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.Type: ApplicationFiled: February 2, 2015Publication date: August 4, 2016Applicant: Agate Logic Inc.Inventors: Kai Keung Chan, David Tsang, Shian-Jiun Fu, Chao-Chiang Chen
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Patent number: 9397680Abstract: A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.Type: GrantFiled: October 31, 2014Date of Patent: July 19, 2016Assignee: eTopus Technology Inc.Inventors: Danfeng Xu, Kai Keung Chan, Yu Kou
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Publication number: 20160197702Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.Type: ApplicationFiled: March 14, 2016Publication date: July 7, 2016Inventors: Kai Keung Chan, Danfeng Xu, Yu Kou
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Publication number: 20160126970Abstract: A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.Type: ApplicationFiled: October 31, 2014Publication date: May 5, 2016Inventors: Danfeng Xu, Kai Keung Chan, Yu Kou
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Patent number: 9319249Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.Type: GrantFiled: August 27, 2014Date of Patent: April 19, 2016Assignee: eTopus Technology Inc.Inventors: Kai Keung Chan, Danfeng Xu, Yu Kou
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Publication number: 20160065396Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.Type: ApplicationFiled: August 27, 2014Publication date: March 3, 2016Inventors: Kai Keung Chan, Danfeng Xu, Yu Kou
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Patent number: 9043688Abstract: Generating error data associated with decoding data is disclosed, including: processing an input sequence of samples associated with data stored on media using a detector and a decoder during a global iteration; and generating one or more error values based at least in part on one or more decision bits output by the detector or the decoder and the input sequence of samples.Type: GrantFiled: March 22, 2012Date of Patent: May 26, 2015Assignee: SK hynix memory solutions inc.Inventors: Kai Keung Chan, Xin-Ning Song, Jason Bellorado, Kwok W. Yeung
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Patent number: 8981813Abstract: A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.Type: GrantFiled: November 29, 2012Date of Patent: March 17, 2015Assignee: Agate Logic, Inc.Inventors: Kai Keung Chan, David Tsang, Shian-Jiun Fu, Chao-Chiang Chen
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Patent number: 8935309Abstract: A signal is generated by obtaining an unconstrained random bit sequence. The unconstrained random bit sequence is modified to satisfy a constraint and the modified random bit sequence is output.Type: GrantFiled: April 12, 2012Date of Patent: January 13, 2015Assignee: SK hynix memory solutions inc.Inventors: Kai Keung Chan, Xin-Ning Song