Patents by Inventor Kai Liao

Kai Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12369042
    Abstract: A method of efficient wideband operation for intra-band non-contiguous spectrum using extending bandwidth part (BWP) configuration is proposed. The BWP definition is extended to cluster BWPs to aggregate distributed spectrum blocks within a frequency range (e.g., 200 MHz) by single carrier operation and facilitate UE to filter out the transmission of unknown RAT between any two of the distributed spectrum blocks. In addition, the cluster BWP configuration enables dynamic aggregation of the number and location of the distributed spectrum blocks based on LBT results in unlicensed spectrum. Specifically, the BWP definition is extended to a group of one or multiple radio resource clusters, each of which contains a set of contiguous PRBs in frequency domain within the associated carrier.
    Type: Grant
    Filed: March 13, 2024
    Date of Patent: July 22, 2025
    Assignee: MediaTek Inc.
    Inventor: Pei-Kai Liao
  • Publication number: 20250233200
    Abstract: A solid lithium-ion battery includes a solid electrolyte and a cathode. The cathode, formed on the surface of the solid electrolyte, includes lithium-metal chloride. The cathode has an alloy and an artificial solid electrolyte interphase layer. Thus, an interface between the solid electrolyte and the cathode has better wettability.
    Type: Application
    Filed: June 14, 2024
    Publication date: July 17, 2025
    Inventors: YU-KAI LIAO, SHU-FEN HU, RU-SHI LIU, SUNG-TING YAO
  • Publication number: 20250233570
    Abstract: A resonator chip and a manufacturing method thereof are provided. The manufacturing method of the resonator chip includes the following steps. A quartz wafer is provided. The quartz wafer has a first surface and a second surface opposite to the first surface. A first etching process is performed on the quartz wafer to form multiple inverted mesa portions, and the inverted mesa portions has a first thickness. The quartz wafer is singulated to form multiple resonator chips. Each of the resonator chips includes one of the inverted mesa portions. A second etching process is performed on the resonator chips to form chamfers at edges of the resonator chips.
    Type: Application
    Filed: March 26, 2024
    Publication date: July 17, 2025
    Applicant: TXC Corporation
    Inventors: Wen Yang Chung, Jing-Kai Liao, Jun-Xiang Zeng, Yu Wen Feng, Chi-Fei Su, Tzu-Hsiu Peng
  • Patent number: 12363692
    Abstract: A method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE receives, from a base station, one or more BWP configurations for configuring a plurality of BWPs at the UE. The respective one or more BWP parameters of a set of BWP parameters define each respective BWP of the plurality of BWPs. The UE sends a capability indication indicating that the UE is capable of resetting values of one or more parameters of the set of BWP parameters. The UE sends a subset indication indicating that the UE is capable of resetting values of one or more parameters of a subset of BWP parameters from the set of BWP parameters.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: July 15, 2025
    Assignee: MEDIATEK INC.
    Inventors: Wei-De Wu, Pei-Kai Liao, Din-Hwa Huang, Tsang-Wei Yu
  • Patent number: 12363969
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.
    Type: Grant
    Filed: January 5, 2024
    Date of Patent: July 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
  • Publication number: 20250194269
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip comprising a first photodetector arranged in a first substrate. The first photodetector absorbs light in a first wavelength range. A second substrate underlies the first substrate. A second photodetector is arranged on the second substrate. The second photodetector absorbs light in a second wavelength range different from the first wavelength range. A dielectric structure is arranged between a first surface of the first substrate and a first surface of the second substrate.
    Type: Application
    Filed: February 14, 2025
    Publication date: June 12, 2025
    Inventors: Hsiang-Lin Chen, Yi-Shin Chu, Yin-Kai Liao, Sin-Yi Jiang, Sung-Wen Huang Chen
  • Publication number: 20250168649
    Abstract: Various solutions for multi-radio access technology (RAT) spectrum sharing in mobile communications are described. An apparatus utilizing a first RAT may transmit user equipment (UE) capability information to a first network node of the first RAT, wherein the UE capability information indicates that the apparatus supports multi-RAT spectrum sharing (MRSS). Then, the apparatus may receive a signaling from the first network node, wherein the signaling indicates the apparatus to provide channel information for MRSS. Based on the signaling, the apparatus may perform at least one of the following: (i) transmitting a measurement report of a channel state information-reference signal (CSI-RS) of a second RAT to the first network node; and (ii) transmitting a sounding reference signal (SRS) or a physical random access channel (PRACH) to a second network node of the second RAT.
    Type: Application
    Filed: September 30, 2024
    Publication date: May 22, 2025
    Inventors: Yi-Chia Lo, Din-Hwa Huang, Cheng-Hsun Li, Wei-De Wu, Pei-Kai Liao
  • Patent number: 12288491
    Abstract: A display detection device includes a panel, a detection board, and a detection adapter board. The panel is configured to display. The detection board is coupled to the panel, and is configured to input a detection signal. The detection adapter board is coupled to the panel, and is configured to respond to the detection signal to generate a detection result.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: April 29, 2025
    Assignee: AUO CORPORATION
    Inventors: Te-Sheng Chen, June-Woo Lee, Bo-Kai Liao, Mei-Yi Li, Yu-Chieh Kuo, Chun-Chang Hung, Shang-Chieh Chou, You-Ru Lyu, Yu-Hsun Lin, Chun-Shuo Chen
  • Patent number: 12261190
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a first substrate comprising a first semiconductor material. A first light sensor is disposed within the first substrate. The first light sensor is configured to absorb electromagnetic radiation within a first wavelength range. A second light sensor is disposed within an absorption structure underlying the first substrate. The second light sensor is configured to absorb electromagnetic radiation within a second wavelength range different from the first wavelength range. The absorption structure underlies the first light sensor and comprises a second semiconductor material different from the first semiconductor material.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Lin Chen, Yi-Shin Chu, Yin-Kai Liao, Sin-Yi Jiang, Sung-Wen Huang Chen
  • Publication number: 20250091126
    Abstract: A magnetic component is adapted to be used in a power inductor. The magnetic component includes a magnetic body containing amorphous magnetic powders and/or nano-crystalline magnetic powders and at least one silicon-free glass material distributed among the amorphous magnetic powders and/or nano-crystalline magnetic powders; a coil embedded in the magnetic body; and a pair of electrodes electrically connected to two terminals of the coil, respectively.
    Type: Application
    Filed: November 29, 2024
    Publication date: March 20, 2025
    Inventors: Chih Hung Wei, Chung Kai Liao
  • Publication number: 20250070500
    Abstract: A cable assembly, configured to be mounted to a circuit board having a first conductive pad and a second conductive pad, includes a first cable, a second cable and a support member. The first cable includes a first core, a first insulator and a first shielding layer. The second cable includes a second core, a second insulator and a second shielding layer. The first core and the second core are configured to be in contact with the first conductive pad and the second conductive pad. The support member includes a support portion. The support portion is configured to support the first insulator and the second insulator. The connection portion is in contact with the first shielding layer and the second shielding layer. A cable connector having the cable assembly is also disclosed.
    Type: Application
    Filed: April 29, 2024
    Publication date: February 27, 2025
    Applicant: Luxshare Precision Industry Company Limited
    Inventors: Cheng-Kai LIAO, Wei WANG, Minquan YU, Po-Chang HUANG, Ming-Yu HO
  • Publication number: 20250048763
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.
    Type: Application
    Filed: October 21, 2024
    Publication date: February 6, 2025
    Inventors: Hsiang-Lin Chen, Yi-Shin Chu, Yin-Kai Liao, Sin-Yi Jiang, Kuan-Chieh Huang, Jhy-Jyi Sze
  • Publication number: 20250023961
    Abstract: The application provides a wireless communication method and device for spatial reuse. A heading information of a current-received data packet is decoded by a spatial reuse (SR) initiator device. Based on a decoding result, the SR initiator device determines to initiate SR. The SR initiator device drops the current-received data packet. The SR initiator device transmits a dummy leading signal to a SR response device. The SR initiator device transmits a spatial reuse data packet to the SR response device.
    Type: Application
    Filed: June 14, 2024
    Publication date: January 16, 2025
    Inventors: Tsung-Hsuan WU, Po-Chun FANG, Hsiao-Kai LIAO
  • Publication number: 20250015278
    Abstract: Disclosed is an all-solid-state lithium battery, characterized in that an anode of the all-solid-state lithium battery comprises solid lithium metal, a solid-state electrolyte of the all-solid-state lithium battery comprises lithium lanthanum zirconium oxide, and a joint interface region between the anode and the solid-state electrolyte contains at least lithium nitride and lithium alloy.
    Type: Application
    Filed: September 15, 2023
    Publication date: January 9, 2025
    Applicant: CPC CORPORATION, TAIWAN
    Inventors: Shih-An LIU, Yu-Kai LIAO, Shu-Fen HU, Kevin IPUTERA, Ru-Shi LIU, Jui-Hsiung HUANG
  • Publication number: 20250015102
    Abstract: Some embodiments relate to an integrated circuit light sensor device. The integrated circuit light sensor device includes a semiconductor substrate, as well as a plurality of first light-absorption regions and a plurality of second light-absorption regions located in the semiconductor substrate. Each of the first light-absorption regions includes an implantation region of the semiconductor substrate. The implantation region and the semiconductor substrate form at least a portion of a corresponding one of a plurality of first photodetectors for a first light wavelength band. Each of the second light-absorption regions includes a semiconductor material different from the semiconductor substrate. The semiconductor material forms at least a portion of a corresponding one of a plurality of second photodetectors for a second light wavelength band different from the first light wavelength band.
    Type: Application
    Filed: July 3, 2023
    Publication date: January 9, 2025
    Inventors: Hsiang-Lin Chen, Yi-Shin Chu, Yin-Kai Liao, Sin-Yi Jiang, Sung-Wen Huang Chen
  • Patent number: 12166054
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Lin Chen, Yi-Shin Chu, Yin-Kai Liao, Sin-Yi Jiang, Kuan-Chieh Huang, Jhy-Jyi Sze
  • Publication number: 20240387587
    Abstract: A semiconductor image sensor includes a first substrate including a first front side and a first back side, and a second substrate including a second front side and a second back side. The first substrate includes a layer and a first light-sensing element in the layer. The layer includes a first semiconductor material, and the first light-sensing element includes a second semiconductor material. The second substrate is bonded to the first substrate with the second front side facing the first back side.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: JHY-JYI SZE, YI-SHIN CHU, YIN-KAI LIAO, HSIANG-LIN CHEN, SIN-YI JIANG, KUAN-CHIEH HUANG
  • Publication number: 20240387766
    Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Inventors: Jhy-Jyi Sze, Sin-Yi Jiang, Yi-Shin Chu, Yin-Kai Liao, Hsiang-Lin Chen, Kuan-Chieh Huang
  • Patent number: 12148853
    Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.
    Type: Grant
    Filed: November 29, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jhy-Jyi Sze, Sin-Yi Jiang, Yi-Shin Chu, Yin-Kai Liao, Hsiang-Lin Chen, Kuan-Chieh Huang
  • Publication number: 20240372028
    Abstract: A method of manufacturing a semiconductor structure includes: forming a light-absorption layer in a substrate, wherein the light-absorption layer includes an upper surface above an upper surface of the substrate; forming a first doped region and a second doped region in the light-absorption layer adjacent to the first doped region; depositing a first patterned mask layer over the light-absorption layer, wherein the first patterned mask layer includes an opening exposing the second doped region and covers the first doped region; forming a first silicide layer in the opening on the second doped region; and forming a second silicide layer on the first doped region.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: YI-SHIN CHU, HSIANG-LIN CHEN, YIN-KAI LIAO, SIN-YI JIANG, KUAN-CHIEH HUANG