Abstract: Provided are a method and an apparatus for lens focusing, a computer device, and a storage medium. The method includes: acquiring a test image obtained by a lens shooting a reference image at a current focusing position, and determining a low-frequency modulation transfer function value of the test image; in response to determining that the low-frequency modulation transfer function value meets a preset value range condition, determining a high-frequency modulation transfer function value of the test image, determining a movement step according to the high-frequency modulation transfer function value, and controlling the lens to move according to the movement step; and using the next focusing position which the lens moves to according to the movement step as a new current focusing position to focus the lens for one time.

Abstract: An apparatus for inspecting a semiconductor substrate includes a rotatable base configured to support a substrate, and a nozzle arm includes a nozzle and a light monitoring device. The light monitoring device includes a laser transmitter and an array of light sensors arranged in the nozzle arm and facing the substrate. The light monitoring device is configured to transmit a laser pulse towards the substrate, wherein the laser pulse impinges on the substrate, receive a reflected laser pulse from the substrate, calculate whether one or more light sensors received the laser pulse, and calculate a distance between the light monitoring device and the substrate using the turnaround time for determining a process quality on the substrate.

Abstract: The present invention relates to a pharmaceutical composition useful for treating a Respiratory Syncytial Virus (RSV) infection, comprising a compound which is or a pharmaceutically acceptable salt thereof, and a second anti-respiratory syncytial virus agent.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: A power supply includes a conversion circuit, an auxiliary power circuit, and an output control circuit. The conversion circuit converts a DC power into a first output power, and the auxiliary power circuit converts the DC power into a first auxiliary power. The output control circuit is used to selectively connect a first output terminal and a second output terminal so that when the output control circuit disconnects the first output terminal and the second output terminal, the first output power supplies power to a critical load through the first output terminal, and when the output control circuit connects the first output terminal and the second output terminal, the first output power supplies power to the critical load and a non-critical load through the first output terminal and the second output terminal respectively.

Abstract: An exposure tool is configured to remove contaminants and/or prevent contamination of mirrors and/or other optical components included in the exposure tool. In some implementations, the exposure tool is configured to flush and/or otherwise remove contaminants from an illuminator, a projection optics box, and/or one or more other subsystems of the exposure tool using a heated gas such as ozone (O3) or extra clean dry air (XCDA), among other examples. In some implementations, the exposure tool is configured to provide a gas curtain (or gas wall) that includes hydrogen (H2) or another type of gas to reduce the likelihood of contaminants reaching the mirrors included in the exposure tool. In this way, the mirrors and one or more other components of the exposure tool are cleaned and maintained in a clean environment in which radiation absorbing contaminants are controlled to increase the performance of the exposure tool.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: The present disclosure provides methods, devices, apparatus, and storage medium for performing speech-to-text conversion. The method includes: displaying, by a first device, a first user interface, the first user interface being a display screen of a virtual environment that provides a virtual activity place for a first virtual role controlled by a first user account; displaying, by a second device, a second user interface, the second user interface being a display screen of a virtual environment that provides a virtual activity place for a second virtual role controlled by a second user account; in response to a speech input operation by the first user account performed on the first device, displaying, by the first device, a chat message in a first language, and displaying, by the second device, the chat message in a second language.

Abstract: A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.

Abstract: A semiconductor chiplet device includes a first die, a second die, a decoupling circuit and an interposer. The interposer includes a plurality of power traces and a plurality of ground traces. The first die and the second die are arranged on a first side of the interposer according to a configuration direction, and are coupled to the power traces and the ground traces. The decoupling circuit is arranged on a second side of the interposer, and is coupled to the power traces and the ground traces. The power traces and the ground traces are staggered with each other, and an extending direction of the ground traces and the power traces is the same as the configuration direction.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a first capacitor conductor disposed over an isolation structure arranged within a substrate. The isolation structure laterally extends past opposing outer sidewalls of the first capacitor conductor. A capacitor dielectric is arranged along one of the opposing outer sidewalls of the first capacitor conductor and over a top surface of the first capacitor conductor. A second capacitor conductor is arranged along an outer sidewall of the capacitor dielectric and over a top surface of the capacitor dielectric. The second capacitor conductor laterally overlaps parts of both the capacitor dielectric and the first capacitor conductor.

Abstract: A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.

Abstract: Provided by the present disclosure is a power distribution box having a data interaction function, comprising a moving mechanism, a control mechanism and a data interaction mechanism. The moving mechanism comprises an electric valve and an electric telescopic rod. The control mechanism comprises a main control single-chip microcomputer and a control panel. The data interaction mechanism comprises a power distribution box tester and an output port. The electric valve is electrically connected to the main control single-chip microcomputer and is arranged at the bottom of the power distribution box. The control panel is arranged on a support rod and is electrically connected to the main control single-chip microcomputer. The power distribution box tester is electrically connected to the main control single-chip microcomputer and is arranged in the power distribution box, and the power distribution box tester is used for testing electrical devices of the power distribution box.

Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.

Abstract: The present invention discloses a set of novel epigenetic biomarkers for early prediction, treatment response, recurrence and prognosis monitoring of pancreatic cancer. Aberrant methylation of genes can be detected in tumor tissues and plasma samples from pancreatic cancer patients but not in normal healthy individual. The present disclosure also discloses primers and probes used herein.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

Abstract: A panel transfer device according to one or more embodiment may include a base; an arm rotatably connected to the base, which includes a first detector; an end effector connected to the arm, including: a connector rotatably connected to the arm; a wrist connected to the connector, including a second detector; and a pair of forks connected to the wrist, including sensor. In response to the end effector gripping the panel, the sensor detects displacement of the panel in a first direction, the end effector rotates to a position where the first and second detectors face each other, the first and second detectors communicate to detect displacement of the panel in a second direction, and the panel transfer device calculates a correction amount based on the detected displacement of the panel in the first direction and in the second direction, and places the panel based on the correction amount.

Abstract: Cleaning tools for cleaning the pull cable of an ingot puller apparatus and methods for cleaning the pull cable are disclosed. The cleaning tool includes a chamber for receiving the pull cable. Pressurized fluid is discharged through one or more nozzles to detach debris from the pull cable. The fluid and debris are collected in an exhaust plenum of the cleaning tool and are expelled through an exhaust tube. The cleaning tool includes one or more guides that guide the cleaning tool in an upper segment of the ingot puller apparatus.

Abstract: This disclosure relates to cathode active materials for use in lithium-ion battery cells.