Abstract: Semiconductor packages and methods of forming the same are disclosed. An semiconductor package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

Abstract: A chromaticity measurement method and device for calibration of a tiled LED display screen (A) having the advantages of convenience in operation and accurate measurement. The chromaticity measurement method includes: imaging emergent light from the tiled LED display screen (A) with an objective lens (1); receiving a light beam from the objective lens (1) with a transflective lens (2) and performing beam splitting to obtain a first light beam and a second light beam; receiving the first light beam with an imaging sensor (3) to obtain an original image; receiving the second light beam in a two-dimensional lattice form with a movable optical fiber array coupling device (4), and converting the second light beam into one-dimensional lattice light; and obtaining chromaticity information and spectrum information of a plurality of regions on the tiled LED display screen (A) according to the one-dimensional lattice light with a spectrum acquisition device (5).

Abstract: A pixel driving circuit includes: a driving transistor, a data write circuit, a threshold compensation circuit, a first capacitor, and a second capacitor. A gate of the driving transistor is coupled to a first node, a first electrode is coupled to a second node, and a second electrode is coupled to a third node. The data write circuit is configured to transmit a signal of a data signal terminal to the second node in response to a signal of a first gate driving signal terminal. The threshold compensation circuit is configured to communicate the first node with the third node in response to a signal of a second gate driving signal terminal. The first capacitor is coupled between the first node and the first gate driving signal terminal. The second capacitor is coupled between the first node and the second gate driving signal terminal.

Abstract: This application relates to an electric vehicle, a thermal management system, and a method for controlling same. The thermal management system includes: a passenger compartment thermal management subsystem, including a compressor, a first throttle, and an evaporator configured to refrigerate the passenger compartment, where the compressor, the first throttle, and the evaporator are controlled to communicate with each other in sequence to form a first refrigerant circuit, the passenger compartment thermal management subsystem further includes a condenser, and the condenser is disposed between the compressor and the first throttle and able to exchange heat with the first refrigerant circuit; a heat emitting component thermal management subsystem, including a heat emitting component and a cooling water tank configured to cool the heat emitting component, and a control valve system, connected to the passenger compartment thermal management subsystem and the heat emitting component thermal management subsystem.

Abstract: A photogrammetric ground control point quality evaluation method based on Monte Carlo test relates to the field of photogrammetry technology. Firstly, aerial photographs and ground control points from a survey area are obtained, the ground control points are numbered, the aerial photographs are performed with point-placing and aerial triangulation densification. Secondly, a Monte Carlo test experiment is designed, a certain number of the ground control points are selected as control points with the rest as check points, ensuring each ground control point as the control point a certain number of times, and average errors of the ground control points are calculated. Thirdly, average values of the average errors of the ground control points are calculated, standard deviations of the average errors of the ground control points are calculated. Finally, a quality coefficient Q of each ground control point is calculated and evaluated according to quality evaluation standards.

Abstract: A method of video processing includes making a determination for a conversion between a video region of a video and a bitstream representation of the video to use a cross-component adaptive loop filtering (CC-ALF) tool for refining chroma samples values using luma sample values; and performing the conversion based on the determination, wherein the refining includes correcting the chroma sample values using a final refinement that is a further refinement of a first refinement value determined by selectively filtering the luma sample values.

Abstract: In an aspect, an apparatus is disclosed that includes a surface-mounted integrated circuit package housing an active oscillator circuit; an integrated ceramic resonator formed from a ceramic substrate having an upper planar surface receiving the surface-mounted integrated circuit package, the integrated ceramic resonator including a plurality of conductive walls forming a conductive periphery of a ceramic cavity in the ceramic substrate, a conductive rod extending vertically into the ceramic cavity, wherein the conductive rod is isolated from contact with the conductive periphery of the ceramic cavity, a first conductive material extending vertically through the upper planar surface of the ceramic substrate for connecting the conductive periphery of the ceramic cavity to the surface-mounted integrated circuit package housing the active oscillator circuit; and a second conductive material extending through the upper planar surface of the ceramic substrate for connecting the conductive rod to the surface-mounte

Abstract: A test socket for 224 Gbps ultra-high-speed coaxial testing includes a test socket body made of metal and a test socket cover plate. The test socket body is provided with mounting holes, within which are set first polymer positioning parts that match the holes. The first polymer positioning part is provided with first and second insertion holes, into which test probes are respectively inserted. The test socket cover plate is fixedly provided with a second polymer positioning part, which has a first positioning hole that matches the first polymer positioning part, and a second positioning hole that is connected to the first positioning hole and matches the end of the test probe. The height of the first polymer positioning part is less than the length of the test probe, achieving a large dynamic bandwidth and high isolation for the coaxial test socket for ultra-high-speed testing frequencies.

Abstract: Disclosed in the embodiments of the present disclosure are a video generation method, an apparatus, an electronic device and a storage medium. The method comprises: during an image editing process of subjecting an initial image to a series of image editing operations to obtain a target image, acquiring initial key frames, the initial key frames being intermediate images between the initial image and the target image during the image editing process, the different initial key frames being intermediate images generated when different image editing operations of the series of image editing operations are triggered during the image editing process, and the intermediate images showing editing effects corresponding to the image editing operations; and generating a target video according to the initial key frames so as to record the image editing process of the target image. The present disclosure can be used for recording an image editing process.

Abstract: A method for video processing is provided. The method includes making a determination, for a conversion between a current video block of a video and a coded representation of the current video block, of whether to use a symmetric motion vector difference (SMVD) mode based on a currently selected best mode for the conversion; and performing the conversion based on the determining.

Abstract: A method of preparing a high-aluminum boron-containing die steel for severe plastic deformation of zinc alloys at elevated temperature, in which a cast ingot is obtained by sand casting, and then subjected to homogenization, austenitization, hot-die forging and cooling to obtain a heat-treated piece. The heat-treated piece is quenched and tempered to obtain a forged piece, which is subjected to finish machining to obtain the high-aluminum boron-containing die steel. A high-aluminum boron-containing die steel prepared by such method is further provided.

Abstract: A power converter includes a power conversion circuit, a bus capacitor, and a controller. A direct current input end of the power conversion circuit is configured to connect to a direct current power supply through a direct current bus. An alternating current output end of the power conversion circuit is configured to connect to an alternating current power grid through a point of common coupling (PCC). The controller is configured to: in response to that a difference between a voltage across two ends of the positive bus capacitor and a voltage across two ends of the negative bus capacitor is greater than a specified threshold, control the power converter to inject a second harmonic current into the alternating current power grid, to reduce the difference between the voltage across the two ends of the positive bus capacitor and the voltage across the two ends of the negative bus capacitor.

Abstract: Embodiments of present disclosure provides methods for determining a fault of a power system. Methods include estimating, based on measured electrical quantities at a first position of a power line in the power system, voltages at a second position of the power line, the measured electrical quantities being associated with three phases of the power system and comprising voltages at the first position of the power line. The methods include determining at least one phase angle between the voltages at the first position and the estimated voltages at the second position, and detecting the fault based on the at least one phase angle during a power swing. In a method according to the present disclosure, a three-phase fault during a power swing is identified in a shorter time, and thus the tripping is performed with a faster speed.

Abstract: A device comprising (i) a first device portion comprising: a die substrate; at least one first dielectric layer; a first plurality of interconnects; a first encapsulation layer; and a first plurality of via interconnects located at least in the first encapsulation layer; (ii) a second device portion comprising: at least one second dielectric layer; a second plurality of interconnects; a second encapsulation layer; and a second plurality of via interconnects located at least in the second encapsulation layer; and (iii) a first plurality of solder interconnects coupled to the first device portion and the second device portion, wherein the first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects and the second plurality of via interconnects are configured to operate as an inductor.

Abstract: A method and apparatus for supporting communication buffer status reports (BSRs) are disclosed. A wireless device may transmit a first buffer status report (BSR) and a second BSR in a medium access control (MAC) protocol data unit (PDU) to a first base station. In an example, the first BSR may be associated with first data for transmission to the wireless device from at least one wireless transmit/receive unit (WTRU). Also, the second BSR may be associated with second data for transmission to the first base station from the wireless device. Further, the wireless device may receive at least a portion of the first data from the at least one WTRU. Moreover, the wireless device may transmit at least a portion of the second data to the first base station. In a further example, the transmitting the first BSR and the second BSR may be based on a priority associated with the first BSR and a priority associated with the second BSR.

Abstract: A door hinge assembly includes a hinge plate and a mounting shaft. The hinge plate includes a mounting plate, a reinforcing plate, and a connecting hook. The reinforcing plate and the connecting hook are each assembled on the mounting plate. The connecting hook is pivotally connected to the mounting shaft. The door hinge assembly further includes a positioning member, and the positioning member is configured to be capable of positioning the mounting plate and/or the reinforcing plate to a cabinet or a door. By providing the positioning member capable of positioning the hinge plate to the cabinet or the door, when the hinge plate is mounted, the hinge plate may first be positioned to the cabinet or the door by the positioning member, and then the hinge plate is tightened by a fastener, so that the assembly efficiency of the door hinge assembly may be increased.

Abstract: A semiconductor package comprises: a package substrate having a front surface and a rear surface, wherein the package substrate comprises: a plurality sets of front conductive patterns; a plurality sets of rear conductive patterns; and a plurality sets of interconnects electrically coupling the set of front conductive patterns with the set of rear conductive patterns, respectively; wherein the package substrate at least comprises a first thermal performance region and a second thermal performance region, wherein the first thermal performance region and the second thermal performance region have different thermal performances; a plurality sets of conductive components attached to the front surface and the rear surface of the package substrate and connected to the plurality sets of front conductive patterns and the plurality sets of rear conductive patterns, wherein the plurality sets of conductive components comprise: a set of first-type conductive components mounted to the first thermal performance region of

Abstract: A semiconductor package comprises: a package substrate having a front surface and a rear surface, wherein the package substrate comprises: a plurality sets of front conductive patterns formed on the front surface; and a plurality sets of interconnects electrically coupled to the plurality sets of front conductive patterns, respectively; a plurality of electronic components mounted to the front surface of the package substrate and electrically coupled to the plurality sets of front conductive patterns via a plurality sets of front conductive components, respectively; wherein the plurality sets of conductive components at least comprise a set of first-type conductive components and a set of second-type conductive components, wherein the set of first-type conductive components are connected to a first electronic component of the plurality of electronic components, and the set of second-type conductive components are connected to a second electronic component of the plurality of electronic components; and wherein

Abstract: An inductive device includes a first set of conductive lines, a second set of conductive lines, and conductive pillars connecting the first set of conductive lines to the second set of conductive lines to form an integrated inductor. The inductive device also includes one or more magnetic layers extending along a length of the integrated inductor and within an aperture of the integrated inductor.

Abstract: A semiconductor package comprise: a package substrate having a front surface and a rear surface, wherein the package substrate comprises: a set of front conductive patterns formed on the front surface; a set of rear conductive patterns formed on the rear surface; and a set of interconnects electrically coupling the set of front conductive patterns with the set of rear conductive patterns, respectively; at least one electronic component mounted on the front surface of the package substrate and electrically coupled to the set of front conductive patterns via a set of front solder balls; a set of rear solder balls electrically connected to the set of rear conductive patterns, respectively; wherein the set of front solder balls comprises one or more first-type solder balls and one or more second-type solder balls, and the set of rear solder balls comprises one or more first-type solder balls and one or more second-type solder balls; and wherein the first-type solder balls of the set of front solder balls are elec