Patents by Inventor Kai-Lou Huang

Kai-Lou Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200212048
    Abstract: The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern.
    Type: Application
    Filed: January 27, 2019
    Publication date: July 2, 2020
    Inventors: Gang-Yi Lin, Shih-Fang Tzou, Fu-Che Lee, Feng-Yi Chang, Ying-Chih Lin, Kai-Lou Huang, Yi-Ching Chang
  • Patent number: 10700071
    Abstract: The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern.
    Type: Grant
    Filed: January 27, 2019
    Date of Patent: June 30, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Gang-Yi Lin, Shih-Fang Tzou, Fu-Che Lee, Feng-Yi Chang, Ying-Chih Lin, Kai-Lou Huang, Yi-Ching Chang
  • Publication number: 20200083325
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.
    Type: Application
    Filed: October 8, 2018
    Publication date: March 12, 2020
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Ching Chang, Kai-Lou Huang, Ying-Chih Lin, Gang-Yi Lin
  • Publication number: 20200083224
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, a first plug, a conductive pad and a capacitor structure. The first plug is disposed on the substrate, and the conductive pad is disposed on the first plug, with the conductive pad including a recessed shoulder portion at a top corner thereof. The capacitor structure is disposed on the conductive pad, to directly in connection with thereto.
    Type: Application
    Filed: October 12, 2018
    Publication date: March 12, 2020
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Ching Chang, Kai-Lou Huang
  • Publication number: 20200083317
    Abstract: A capacitor structure includes a substrate having thereon a storage node contact, a cylinder-shaped bottom electrode disposed on the storage node contact, a supporting structure horizontally supporting a sidewall of the cylinder-shaped bottom electrode, a capacitor dielectric layer conformally covering the cylinder-shaped bottom electrode and the supporting structure, and a top electrode covering the capacitor dielectric layer. The supporting structure has a top surface that is higher than that of the cylinder-shaped bottom electrode. The top surface of the supporting structure has a V-shaped sectional profile.
    Type: Application
    Filed: October 8, 2018
    Publication date: March 12, 2020
    Inventors: Kai-Lou Huang, Fu-Che Lee, Feng-Yi Chang, Chieh-Te Chen, Meng-Chia Tsai