Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region. A source region and a drain region are respectively disposed on each end of the active region along a first direction. A gate trench is formed in the semiconductor substrate between the source region and the drain region, wherein the gate trench includes a sidewall portion and a curved-bottom surface. The curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction perpendicular to the first direction. The gate electrode is disposed in the gate trench and the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate.

Abstract: A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region. A source region and a drain region are respectively disposed on each end of the active region along a first direction. A gate trench is formed in the semiconductor substrate between the source region and the drain region, wherein the gate trench includes a sidewall portion and a curved-bottom surface. The curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction perpendicular to the first direction. The gate electrode is disposed in the gate trench and the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate.