Abstract: A method and apparatus for performing opportunistic refreshes of memory banks is disclosed. Refresh circuitry in a memory controller performs a refresh on each bank of a multi-bank memory at least once during a given refresh interval. At the beginning of an interval, memory banks for which there are no pending transactions (e.g., reads or writes) may be refreshed. During a first portion of the interval, refresh may be skipped for memory banks for which transactions are pending. In a second portion of the interval, refreshes are performed on memory banks that have not been refreshed during the interval, which may cause some memory transactions to be delayed.

Abstract: A method and apparatus for performing opportunistic refreshes of memory banks is disclosed. Refresh circuitry in a memory controller performs a refresh on each bank of a multi-bank memory at least once during a given refresh interval. At the beginning of an interval, memory banks for which there are no pending transactions (e.g., reads or writes) may be refreshed. During a first portion of the interval, refresh may be skipped for memory banks for which transactions are pending. In a second portion of the interval, refreshes are performed on memory banks that have not been refreshed during the interval, which may cause some memory transactions to be delayed.

Abstract: Each processor core in a computing device supports various different frequency ranges, also referred to as p-states, and can operate to run threads at any one of those different frequency ranges. Threads in the computing device are assigned one of multiple importance levels. A processor core is configured to run at a particular frequency range or in accordance with a particular energy performance preference based on the importance level of the thread it is running. A utilization factor of a processor core can also be determined over some time duration, the utilization factor being based on the amount of time during the time duration that the processor core was running a thread(s), and also based on the importance levels of the thread(s) run during the time duration. The utilization factor can then be used to determine whether to park the processor core.

Abstract: Each processor core in a device supports various different frequency ranges and/or energy performance preferences, and can operate to run threads at any one of those different frequency ranges and/or energy performance preferences. Processor cores are partitioned into different groups, each group running at different frequency ranges and/or energy performance preferences. Threads in the device are assigned one of multiple importance levels and scheduled to run on a processor core in a particular group based on the importance level of the thread. Lower importance level threads are scheduled to run in a group that is more power efficient, and higher importance level threads are scheduled to run in a group that is higher performance. The group that a processor core is part of can change during operation of the device based on the needs of the device and/or applications running on the device.

Abstract: Each processor core in a device supports various different frequency ranges and/or energy performance preferences, and can operate to run threads at any one of those different frequency ranges and/or energy performance preferences. Processor cores are partitioned into different groups, each group running at different frequency ranges and/or energy performance preferences. Threads in the device are assigned one of multiple importance levels and scheduled to run on a processor core in a particular group based on the importance level of the thread. Lower importance level threads are scheduled to run in a group that is more power efficient, and higher importance level threads are scheduled to run in a group that is higher performance. The group that a processor core is part of can change during operation of the device based on the needs of the device and/or applications running on the device.

Abstract: Each processor core in a computing device supports various different frequency ranges, also referred to as p-states, and can operate to run threads at any one of those different frequency ranges. Threads in the computing device are assigned one of multiple importance levels. A processor core is configured to run at a particular frequency range or in accordance with a particular energy performance preference based on the importance level of the thread it is running. A utilization factor of a processor core can also be determined over some time duration, the utilization factor being based on the amount of time during the time duration that the processor core was running a thread(s), and also based on the importance levels of the thread(s) run during the time duration. The utilization factor can then be used to determine whether to park the processor core.