Patents by Inventor Kai-Man Chan

Kai-Man Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9844122
    Abstract: Systems and methods are provided for semi-automatic light control systems which support, amongst other features, receiving a light controlling values from one or more users and choosing an optimal light value based on the aggregated preferences of the present users. The lighting elements of the lighting system are further adjusted based on user perception profiles and other parameters. A semi-automatic determination may be made of a second light controlling value based on the first light controlling value and a user perception profile relating light parameter values with perceived light output values. Lighting element operation may be incrementally adjusted to meet the second light parameter value over a predetermined time period.
    Type: Grant
    Filed: January 14, 2017
    Date of Patent: December 12, 2017
    Inventor: Kai Man Chan
  • Publication number: 20030052361
    Abstract: A method for fabricating a triple self-aligned non-volatile memory device is disclosed. The method includes forming isolation oxide on a substrate. A plurality of floating gates are formed by depositing and self-aligning a first polysilicon layer to the isolation oxide. A common source area is then defined on the substrate between the floating gates. A second polysilicon layer is deposited over the common source area and self-aligned with respect to the isolation oxide. A third polysilicon layer is deposited adjacent to the plurality of floating gates. A plurality of select gates are then formed by self-aligning the third polysilicon layer to the isolation oxide. Furthermore, at least one drain area is defined on the substrate.
    Type: Application
    Filed: October 29, 2002
    Publication date: March 20, 2003
    Inventors: Chun-Mai Liu, Kung-Yen Su, Kai-Man Chan, Albert V. Kordesch
  • Patent number: 6492231
    Abstract: A method for fabricating a triple self-aligned non-volatile memory device is disclosed. The method includes forming isolation oxide on a substrate. A plurality of floating gates are formed by depositing and self-aligning a first polysilicon layer to the isolation oxide. A common source area is then defined on the substrate between the floating gates. A second polysilicon layer is deposited over the common source area and self-aligned with respect to the isolation oxide. A third polysilicon layer is deposited adjacent to the plurality of floating gates. A plurality of select gates are then formed by self-aligning the third polysilicon layer to the isolation oxide. Furthermore, at least one drain area is defined on the substrate.
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: December 10, 2002
    Assignee: Winbond Electronics Corporation
    Inventors: Chun-Mai Liu, Kung-Yen Su, Kai-Man Chan, Albert V. Kordesch
  • Publication number: 20020022322
    Abstract: A method for fabricating a triple self-aligned non-volatile memory device is disclosed. The method includes forming isolation oxide on a substrate. A plurality of floating gates are formed by depositing and self-aligning a first polysilicon layer to the isolation oxide. A common source area is then defined on the substrate between the floating gates. A second polysilicon layer is deposited over the common source area and self-aligned with respect to the isolation oxide. A third polysilicon layer is deposited adjacent to the plurality of floating gates. A plurality of select gates are then formed by self-aligning the third polysilicon layer to the isolation oxide. Furthermore, at least one drain area is defined on the substrate.
    Type: Application
    Filed: June 8, 2001
    Publication date: February 21, 2002
    Inventors: Chun-Mai Liu, Kung-Yen Su, Kai-Man Chan, Albert V. Kordesch