Patents by Inventor Kai-Min Chien

Kai-Min Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250031399
    Abstract: A semiconductor device with a barrier layer between a gate structure and gate spacer layers, and a method of fabricating the same are disclosed. The a method includes forming a fin structure on a substrate, forming a polysilicon structure on the fin structure, performing a nitridation operation to form a barrier layer on the polysilicon structure and the fin structure, forming gate spacer layers on the barrier layer, forming a source/drain region in the fin structure and adjacent to the barrier layer, annealing the gate spacer layers, and replacing the polysilicon structure with a gate structure.
    Type: Application
    Filed: July 18, 2023
    Publication date: January 23, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mu-Min Hung, Fan Hsuan Chien, Jyh-Nan Lin, Kai-Shiung Hsu, Tzu-Chien Cheng, Su-Yu Yeh
  • Publication number: 20240355906
    Abstract: Embodiments include a method and device resulting from the method, including using a radical oxidation process to oxidize a spacer layer which lines the opening after removing a dummy gate electrode. The oxidized layer is removed by an etching process. An STI region disposed below the dummy gate electrode may be partially etched.
    Type: Application
    Filed: April 20, 2023
    Publication date: October 24, 2024
    Inventors: Shao-Hua Hsu, Chia-I Lin, Hsiu-Hao Tsao, Kai-Min Chien, Chen-Huang Huang, An Chyi Wei, Ryan Chia-Jen Chen
  • Publication number: 20230187535
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a fin structure protruding from a substrate, and the fin structure includes first semiconductor material layers and second semiconductor material layers alternately stacked. The method also includes forming a dummy gate structure across the fin structure and forming a gate spacer on a sidewall of the dummy gate structure. The method also includes partially oxidizing the gate spacer to form an oxide layer and removing the oxide layer to form a modified gate spacer. The method also includes removing the first semiconductor material layers to form gaps and forming a gate structure in the gaps to wrap around the second semiconductor material layers and over the second semiconductor material layers to cover the modified gate spacer.
    Type: Application
    Filed: June 2, 2022
    Publication date: June 15, 2023
    Inventors: Yu-Jiun Peng, Hsuan-Chih Wu, Cheng-Chung Chang, Shu-Han Chen, Hsiu-Hao Tsao, Min-Chia Lee, Kai-Min Chien, Ming-Chang Wen, Kuo-Feng Yu, Chang-Jhih Syu