Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed adjacent to a metal gate structure (MG), an S/D contact disposed over the S/D feature, and a dielectric layer disposed over the S/D contact, where the S/D feature and the S/D contact are separated from the MG by a first air gap, where the dielectric layer partially fills the first air gap, and where a bottom portion of a bottom surface of the S/D contact is separated from a top portion of the S/D feature by a second air gap that is connected to the first air gap.

Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

Abstract: Some implementations described herein include systems and techniques for fabricating a stacked die product. The systems and techniques include using a supporting fill mixture that includes a combination of types of composite particulates in a lateral gap region of a stack of semiconductor substrates and along a perimeter region of the stack of semiconductor substrates. One type of composite particulate included in the combination may be a relatively smaller size and include a smooth surface, allowing the composite particulate to ingress deep into the lateral gap region. Properties of the supporting fill mixture including the combination of types of composite particulates may control thermally induced stresses during downstream manufacturing to reduce a likelihood of defects in the supporting fill mixture and/or the stack of semiconductor substrates.

Abstract: A data processing circuit and a fault mitigating method are provided. The method is adapted for a memory having at least one fault bit. The memory provides a block for data storage. A difference between an output of a value of a plurality of bits input to at least one computing layer in a neural network and a correct value is determined. The bits are respectively considered the at least one fault bit. A repair condition is determined based on the difference. The repair condition includes a correspondence between a position where the fault bit is located in the block and at least one non-fault bit in the memory. A value of at least one non-fault bit of the memory replaces a value of the fault bit based on the repair condition.

Abstract: Disclosed is a diamine compound represented by Formula (1), in which R1, R2, R3, R4, R5, X1, X2, X3, X4, m, n, a, b, c, and d are as defined herein. Also disclosed are a method for manufacturing the diamine compound, a composition including the diamine compound having a (chain alkoxy-methylene) phenyl group or a (hydroxyl-methylene) phenyl group, and a polymer including the (chain alkoxy-methylene) phenyl group or the (hydroxyl-methylene) phenyl group.

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Abstract: A semiconductor device includes a first metal layer, a second metal layer, and an inter-metal dielectric layer disposed between the first metal layer and the second metal layer. The inter-metal dielectric layer includes: a first dielectric layer disposed on the first metal layer and in direct contact with the first metal layer, wherein the first dielectric layer has a stress value less than 0; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer has a stress value greater than 0; and a third dielectric layer disposed on the second dielectric layer, wherein the third dielectric layer has a stress value less than 0. A thickness of the third dielectric layer is greater than a thickness of the second dielectric layer, and the thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: A semiconductor device includes source/drain regions, a gate structure, a first gate spacer, and a dielectric material. The source/drain regions are over a substrate. The gate structure is laterally between the source/drain regions. The first gate spacer is on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region. The dielectric material is between the first one of the source/drain regions and the void region. The dielectric material has a gradient ratio of a first chemical element to a second chemical element.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.

Abstract: In an example, a system for indicating alignment between two components that are mechanically coupled to each other is disclosed. The system includes a first component, a second component, a connector configured to mechanically couple the first component to the second component by moving the connector from a first position to a second position, a first circuit affixed to the first component, and a second circuit affixed to the connector. The first circuit and the second circuit are positioned on the first component and the connector, respectively, such that an electrical connection between the first circuit and the second circuit occurs when the connector is in the second position and the first component and the second component are aligned. The first circuit or the second circuit comprises an antenna, and the electrical connection enables the antenna to transmit a signal.

Abstract: A coaxially arranged smart susceptor conductor, comprising a smart susceptor core comprising an alloy having a first Curie temperature point and a first smart susceptor shell coaxially arranged around the smart susceptor core. The first smart susceptor shell comprising a second Curie temperature point that is different than the first Curie temperature point of the smart susceptor core. In one arrangement, the second Curie temperature point of the first smart susceptor shell is lower than the first Curie temperature point of the smart susceptor core. In another arrangement, the smart susceptor conductor further comprises a second smart susceptor shell disposed about the first smart susceptor shell. The second smart susceptor shell comprising a third Curie temperature point.

Abstract: In an example, a system for indicating alignment between two components that are mechanically coupled to each other is disclosed. The system includes a first component, a second component, a connector configured to mechanically couple the first component to the second component by moving the connector from a first position to a second position, a first circuit affixed to the first component, and a second circuit affixed to the connector. The first circuit and the second circuit are positioned on the first component and the connector, respectively, such that an electrical connection between the first circuit and the second circuit occurs when the connector is in the second position and the first component and the second component are aligned. The first circuit or the second circuit comprises an antenna, and the electrical connection enables the antenna to transmit a signal.

Abstract: A susceptor wire array. The array includes a first susceptor wire comprising an alloy having a first Curie temperature point and a second susceptor wire comprising an alloy having a second Curie temperature point, the second Curie temperature point is different than the first Curie temperature point of the first susceptor wire. In one susceptor wire arrangement, the second Curie temperature point of the second susceptor wire is lower than the first Curie temperature point of the first susceptor wire. In another susceptor wire arrangement, the array further comprises a third susceptor wire, the third susceptor wire comprising an alloy having a third Curie temperature point. The third Curie temperature point of the third susceptor wire may be different than the first Curie temperature point of the first susceptor wire.

Abstract: Methods and systems for heating forming dies by an induction coil, including a pair of electromagnetic (EM) field stabilizers, each EM field stabilizer configured to be adjacent one end of the forming die while the forming die is within the induction heating coil.

Abstract: A honeycomb thermal insulation structure may comprise a first facesheet, a second facesheet, and a honeycomb core between the first facesheet and the second facesheet. The honeycomb core may include a plurality of honeycomb unit cells each composed of walls having a height and spaced by a distance. The walls of the honeycomb cells may have perforations. The honeycomb thermal insulation structure may further comprise a non-convective gas loaded in the honeycomb unit cells between the walls. A flow of the gas through the perforations may be substantially absent.

Abstract: A coaxially arranged smart susceptor conductor, comprising a smart susceptor core comprising an alloy having a first Curie temperature point and a first smart susceptor shell coaxially arranged around the smart susceptor core. The first smart susceptor shell comprising a second Curie temperature point that is different than the first Curie temperature point of the smart susceptor core. In one arrangement, the second Curie temperature point of the first smart susceptor shell is lower than the first Curie temperature point of the smart susceptor core. In another arrangement, the smart susceptor conductor further comprises a second smart susceptor shell disposed about the first smart susceptor shell. The second smart susceptor shell comprising a third Curie temperature point.