Patents by Inventor Kai-Ming Liu
Kai-Ming Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9747409Abstract: A method performed by at least one processor comprises the steps of: generating a layout data of a chip comprising transistors; determining heat-related parameters for the transistors based on the locations thereof in the layout data; generating a netlist data comprising the heat-related parameters; performing a post-layout simulation based on the netlist data; and verifying whether the post-layout simulation meets a design specification.Type: GrantFiled: September 24, 2015Date of Patent: August 29, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Yang Lin, Kai-Ming Liu
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Publication number: 20170242954Abstract: A method includes the operation below. Groups, indicating layout patterns of interconnection layers, are assigned to a circuit, to determine layout constraints of the circuit. Layout patterns are extracted from a layout design for the circuit. The layout patterns are compared with the layout constraints. Data, indicating the layout design, for fabrication of the circuit are generated in a condition that the layout patterns meet the layout constraints.Type: ApplicationFiled: February 23, 2016Publication date: August 24, 2017Inventors: Yao-Jen HSIEH, Kai-Ming LIU
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Publication number: 20170091371Abstract: A method performed by at least one processor comprises the steps of: generating a layout data of a chip comprising transistors; determining heat-related parameters for the transistors based on the locations thereof in the layout data; generating a netlist data comprising the heat-related parameters; performing a post-layout simulation based on the netlist data; and verifying whether the post-layout simulation meets a design specification.Type: ApplicationFiled: September 24, 2015Publication date: March 30, 2017Inventors: WEI-YANG LIN, KAI-MING LIU
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Patent number: 9582630Abstract: One or more systems and methods for a cell based hybrid resistance and capacitance (RC) extraction are provided. The method includes generating a layout for a semiconductor arrangement, performing a three-dimensional (3D) RC extraction on a target unit cell to obtain a 3D RC result including a coupling capacitance between unit cells, generating a 3D RC netlist based upon the 3D RC result, performing a 2.5 dimensional (2.5D) RC extraction on a peripheral cell to obtain a 2.5D RC netlist, and combining the 3D RC netlist with the 2.5D RC netlist to create a hybrid RC netlist for the layout. In some embodiments, the hybrid RC netlist is generated by stitching the coupling capacitance for at least one of the target unit cell, a repeating unit cell, or the peripheral cell together. In some embodiments, the 3D RC result for the target unit cell is stitched to the repeating unit cell.Type: GrantFiled: August 28, 2014Date of Patent: February 28, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ze-Ming Wu, Shih Hsin Chen, Chien-Chih Kuo, Kai-Ming Liu, Hsien-Hsin Sean Lee
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Patent number: 9495506Abstract: Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.Type: GrantFiled: June 8, 2015Date of Patent: November 15, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih Hsin Chen, Kai-Ming Liu
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Patent number: 9342647Abstract: An integrated circuit design method comprises extracting parallel-connected parameters associated with circuit components of an integrated circuit (IC) based on a determination that the circuit components are connected in parallel. The method also comprises generating a parallel netlist that describes the circuit components, the parallel netlist comprising the parallel-connected parameters. The parallel-connected parameters are taken into consideration by a simulation that determines the performance capabilities of the IC.Type: GrantFiled: April 22, 2014Date of Patent: May 17, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih Hsin Chen, Kai-Ming Liu
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Patent number: 9331066Abstract: A method of detecting a parasitic transistor detecting is provided. The method includes extracting several diodes from a selected area, selecting at least one diode pair from the diodes in accordance with signals connected to the diodes, and filtering the at least one diode pair in accordance with a threshold distance to determine whether at least one parasitic transistor is obtained.Type: GrantFiled: January 24, 2014Date of Patent: May 3, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ming-Huei Tsai, Yao-Jen Hsieh, Kai-Ming Liu
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Publication number: 20160063165Abstract: One or more systems and methods for a cell based hybrid resistance and capacitance (RC) extraction are provided. The method includes generating a layout for a semiconductor arrangement, performing a 3D RC extraction on a target unit cell to obtain a 3D RC result including a coupling capacitance between unit cells, generating a 3D RC netlist based upon the 3D RC result, performing a 2.5D RC extraction on a peripheral cell to obtain a 2.5D RC netlist, and combining the 3D RC netlist with the 2.5D RC netlist to create a hybrid RC netlist for the layout. In some embodiments, the hybrid RC netlist is generated by stitching the coupling capacitance for at least one of the target unit cell, a repeating unit cell, or the peripheral cell together. In some embodiments, the 3D RC result for the target unit cell is stitched to the repeating unit cell.Type: ApplicationFiled: August 28, 2014Publication date: March 3, 2016Inventors: Ze-Ming Wu, Shih Hsin Chen, Chien-Chih Kuo, Kai-Ming Liu, Hsien-Hsin Sean Lee
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Publication number: 20150302136Abstract: Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.Type: ApplicationFiled: June 8, 2015Publication date: October 22, 2015Inventors: Shih Hsin Chen, Kai-Ming Liu
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Publication number: 20150269305Abstract: An integrated circuit design method comprises extracting parallel-connected parameters associated with circuit components of an integrated circuit (IC) based on a determination that the circuit components are connected in parallel. The method also comprises generating a parallel netlist that describes the circuit components, the parallel netlist comprising the parallel-connected parameters. The parallel-connected parameters are taken into consideration by a simulation that determines the performance capabilities of the IC.Type: ApplicationFiled: April 22, 2014Publication date: September 24, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih Hsin CHEN, Kai-Ming LIU
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Publication number: 20150212134Abstract: A method of detecting a parasitic transistor detecting is provided. The method includes extracting several diodes from a selected area, selecting at least one diode pair from the diodes in accordance with signals connected to the diodes, and filtering the at least one diode pair in accordance with a threshold distance to determine whether at least one parasitic transistor is obtained.Type: ApplicationFiled: January 24, 2014Publication date: July 30, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: MING-HUEI TSAI, YAO-JEN HSIEH, KAI-MING LIU
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Patent number: 9053288Abstract: A method includes extracting multiple-patterning group assignment information of one or more layout patterns from a layout design. The layout design corresponds to a circuit design, and the one or more layout patterns corresponding to a node of the circuit design. Whether the extracted multiple-patterning group assignment information is consistent with a set of multiple-patterning group assignment constraints of the node is determined by a hardware processor.Type: GrantFiled: March 31, 2014Date of Patent: June 9, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yao-Jen Hsieh, Kai-Ming Liu
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Patent number: 9053283Abstract: Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.Type: GrantFiled: March 15, 2013Date of Patent: June 9, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih Hsin Chen, Kai-Ming Liu
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Publication number: 20150154339Abstract: Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.Type: ApplicationFiled: March 15, 2013Publication date: June 4, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih Hsin Chen, Kai-Ming Liu
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Method and system for checking the inter-chip connectivity of a three-dimensional integrated circuit
Patent number: 8972916Abstract: A method for checking the inter-chip connectivity of a three-dimensional (3D) integrated circuit (IC) generally comprises receiving a design file for each of a plurality of chips of the 3D IC and generating a plurality of inter-layer ports to be shared between at least two of the of chips based on the design files for each of the chips. A layout without the share ports for each of the chips based on the design files for each of the chips is generated and a layout versus schematic (LVS) check is conducted for each of the generated layouts by using the identified inter-layer ports.Type: GrantFiled: December 5, 2013Date of Patent: March 3, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yao-Jen Hsieh, Kai-Ming Liu -
Patent number: 8943455Abstract: Methods for standard cells using finFET standard cell structures with polysilicon on OD edges. Standard cells are defined using finFET transistors and having gate structures forming a transistor at an intersection with a semiconductor fin. Polysilicon dummy structures are formed on the edges of the active areas or OD areas of the standard cells. In a design flow, a pre-layout netlist schematic for the standard cells includes a three terminal MOS device corresponding to the polysilicon dummy structure on the edges of the standard cell. After an automated place and route process forms a device layout using the standard cells, a post layout netlist is extracted. Where two standard cells abut one another, a single polysilicon dummy structure is formed on the common boundary. A layout versus schematic comparison is then performed comparing the pre-layout netlist and the post-layout netlist to verify the layout obtained. Additional methods are disclosed.Type: GrantFiled: March 15, 2013Date of Patent: January 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih Hsin Chen, Kai-Ming Liu
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Publication number: 20140282325Abstract: Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih Hsin Chen, Kai-Ming Liu
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Publication number: 20140282326Abstract: Methods for standard cells using finFET standard cell structures with polysilicon on OD edges. Standard cells are defined using finFET transistors and having gate structures forming a transistor at an intersection with a semiconductor fin. Polysilicon dummy structures are formed on the edges of the active areas or OD areas of the standard cells. In a design flow, a pre-layout netlist schematic for the standard cells includes a three terminal MOS device corresponding to the polysilicon dummy structure on the edges of the standard cell. After an automated place and route process forms a device layout using the standard cells, a post layout netlist is extracted. Where two standard cells abut one another, a single polysilicon dummy structure is formed on the common boundary. A layout versus schematic comparison is then performed comparing the pre-layout netlist and the post-layout netlist to verify the layout obtained. Additional methods are disclosed.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih Hsin Chen, Kai-Ming Liu
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Patent number: 8743085Abstract: A touch input device for switching driving signals includes a touch panel and a panel driving circuit for driving the touch panel. The panel driving circuit includes a selecting circuit, a driving signal generating circuit, and a touch sensing circuit. The driving signal generating circuit transmits a driving signal to the touch panel. The selecting circuit includes a multiplexer, which controls sensing lines that do not comprise either an X directional measuring channel or a Y directional measuring channel to be grounded or floating in accordance with the driving signal.Type: GrantFiled: May 10, 2012Date of Patent: June 3, 2014Assignee: Raydium Semiconductor CorporationInventors: Kai Ming Liu, Shih Tzung Chou, Ya Ling Lu
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Patent number: D730966Type: GrantFiled: March 4, 2014Date of Patent: June 2, 2015Assignee: D-LINK CORPORATIONInventor: Kai-Ming Liu