Patents by Inventor Kai Oliver Weber
Kai Oliver Weber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7853917Abstract: A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached.Type: GrantFiled: December 21, 2007Date of Patent: December 14, 2010Assignee: International Business Machines CorporationInventors: Viresh Paruthi, Christian Jacobi, Geert Janssen, Jiazhao Xu, Kai Oliver Weber
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Patent number: 7836413Abstract: A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached.Type: GrantFiled: December 21, 2007Date of Patent: November 16, 2010Assignee: International Business Machines CorporationInventors: Viresh Paruthi, Christian Jacobi, Geert Janssen, Jiazhao Xu, Kai Oliver Weber
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Patent number: 7752583Abstract: A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.Type: GrantFiled: November 26, 2007Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Christian Jacobi, Viresh Paruthi, Kai Oliver Weber
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Publication number: 20100146474Abstract: A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached.Type: ApplicationFiled: December 21, 2007Publication date: June 10, 2010Inventors: Viresh Paruthi, Christian Jacobi, Geert Janssen, Jiazhao Xu, Kai Oliver Weber
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Publication number: 20100138805Abstract: A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached.Type: ApplicationFiled: December 21, 2007Publication date: June 3, 2010Inventors: Viresh Paruthi, Christian Jacobi, Geert Janssen, Jiazhao Xu, Kai Oliver Weber
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Publication number: 20090164965Abstract: A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached.Type: ApplicationFiled: December 21, 2007Publication date: June 25, 2009Inventors: Viresh Paruthi, Christian Jacobi, Geert Janssen, Jiazhao Xu, Kai Oliver Weber
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Publication number: 20090164966Abstract: A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached.Type: ApplicationFiled: December 21, 2007Publication date: June 25, 2009Inventors: Viresh Paruthi, Christian Jacobi, Geert Janssen, Jiazhao Xu, Kai Oliver Weber
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Patent number: 7506290Abstract: A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the one or more variables represented by the one or more nodes by setting the first fattest variable to a primary value, and a first cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using an inverse of the primary value to generate a first cofactored binary decision diagram set. A second cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using the primary value to generate a second cofactored binary decision diagram set, and verification of the design is performed by evaluating a property of the second cofactored binary decision diagram set.Type: GrantFiled: December 21, 2007Date of Patent: March 17, 2009Assignee: International Business Machines CorporationInventors: Christian Jacobi, Geert Janssen, Viresh Paruthi, Kai Oliver Weber
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Patent number: 7475371Abstract: A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the one or more variables represented by the one or more nodes by setting the first fattest variable to a primary value, and a first cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using an inverse of the primary value to generate a first cofactored binary decision diagram set. A second cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using the primary value to generate a second cofactored binary decision diagram set, and verification of the design is performed by evaluating a property of the second cofactored binary decision diagram set.Type: GrantFiled: December 21, 2007Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Christian Jacobi, Geert Janssen, Viresh Paruthi, Kai Oliver Weber
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Patent number: 7458048Abstract: A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.Type: GrantFiled: November 26, 2007Date of Patent: November 25, 2008Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Christian Jacobi, Viresh Paruthi, Kai Oliver Weber
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Patent number: 7367001Abstract: A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.Type: GrantFiled: December 2, 2004Date of Patent: April 29, 2008Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Christian Jacobi, Viresh Paruthi, Kai Oliver Weber
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Patent number: 7363603Abstract: A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the one or more variables represented by the one or more nodes by setting the first fattest variable to a primary value, and a first cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using an inverse of the primary value to generate a first cofactored binary decision diagram set. A second cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using the primary value to generate a second cofactored binary decision diagram set, and verification of the design is performed by evaluating a property of the second cofactored binary decision diagram set.Type: GrantFiled: September 13, 2005Date of Patent: April 22, 2008Assignee: International Business Machines CorporationInventors: Christian Jacobi, Geert Janssen, Viresh Paruthi, Kai Oliver Weber
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Patent number: 7340473Abstract: A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached.Type: GrantFiled: August 26, 2004Date of Patent: March 4, 2008Assignee: International Business Machines CorporationInventors: Viresh Paruthi, Christian Jacobi, Geert Janssen, Jiazhao Xu, Kai Oliver Weber
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Patent number: 7290229Abstract: A method for verifying a design through symbolic simulation is disclosed. The method comprises creating one or more binary decision diagram variables for one or more inputs in a design containing one or more state variables and building a binary decision diagram for a first node of one or more nodes of the design. A binary decision diagram for the initial state function of one or more state variables of the design is generated and the design is subsequently initialized. Binary decisions diagrams for one or more constraints are synthesized. A set of constraint values is accumulated over time by combining the binary decision diagrams for the one or more constraints with a set of previously generated binary decision diagrams for a set of constraints previously used in one or more previous time-steps. A binary decision diagram for the next state function of the one or more state variables in the design is constructed in the presence of the constraints.Type: GrantFiled: February 3, 2005Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Christian Jacobi, Viresh Paruthi, Kai Oliver Weber