Abstract: An electrochemical cell and a method of manufacturing the electrochemical cell are provided. The method includes: spraying a precursor solution on an anode, the precursor solution including a metal salt dissolved in a solvent and the anode being at a temperature of 250° C. or greater; reacting the metal salt on the anode to form a buffer layer; and attaching a solid-state electrolyte to the buffer layer.

Abstract: A buffered negative electrode-electrolyte assembly includes: a porous negative electrode comprising a metal, a transition metal nitride, or a combination thereof; a solid-state electrolyte; and a buffer layer between the porous negative electrode and the solid-state electrolyte. The buffer layer comprising a buffer composition according to Formula (1) MmNnZzHhXx. The buffer composition has an electronic conductivity that is less than or equal to 1×10-2 times an electronic conductivity of the solid-state electrolyte, and the buffer composition has an ionic conductivity less than or equal to 1×10-6 times an ionic conductivity of the solid-state electrolyte.

Abstract: A buffered negative electrode-electrolyte assembly includes: a porous negative electrode comprising a metal, a transition metal nitride, or a combination thereof; a solid-state electrolyte; and a buffer layer between the porous negative electrode and the solid-state electrolyte. The buffer layer comprising a buffer composition according to Formula (1) MmNnZzHhXx. The buffer composition has an electronic conductivity that is less than or equal to 1×10?2 times an electronic conductivity of the solid-state electrolyte, and the buffer composition has an ionic conductivity less than or equal to 1×10?6 times an ionic conductivity of the solid-state electrolyte.

Abstract: A display panel includes a first substrate, a second substrate, a light-emitting diode, a white insulation layer, and a first spacer layer. The first substrate has a filter layer and at least one black matrix. The second substrate is opposite to the first substrate. The light-emitting diode is disposed on the second substrate. The white insulation layer is located on the first substrate and protrudes toward the second substrate. The white insulation layer is overlapped with the filter layer and the black matrix along a first direction substantially perpendicular to the first substrate. The first spacer layer is disposed between the second substrate and the white insulation layer, and the first spacer layer is overlapped with the black matrix along the first direction.

Abstract: A display panel includes a first substrate, a second substrate, at least one light-emitting diode, at least one reflective layer, and at least one first spacer layer. The first substrate has a filter layer. The second substrate is opposite to the first substrate. The light-emitting diode is disposed on the second substrate. The reflective layer is located on the first substrate and protrudes toward the second substrate. The first spacer layer is located between the first substrate and the second substrate. The first spacer layer has a first end and a second end, and the first end of the first spacer layer is located between a surface of the reflective layer adjacent to the second substrate and the second substrate.

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include performing, using a processor, an electronic design process on a portion of an electronic design. Embodiments may also include automatically monitoring the electronic design process on a periodic basis using a pulse monitor to acquire one or more sampling results and storing the one or more sampling results. Embodiments may further include providing, during the electronic design process, the one or more sampling results to a graphical user interface.

Abstract: A buffered negative electrode-electrolyte assembly includes: a porous negative electrode comprising a metal, a transition metal nitride, or a combination thereof; a solid-state electrolyte; and a buffer layer between the porous negative electrode and the solid-state electrolyte. The buffer layer comprising a buffer composition according to Formula (1) MmNnZzHhXx. The buffer composition has an electronic conductivity that is less than or equal to 1×10?2 times an electronic conductivity of the solid-state electrolyte, and the buffer composition has an ionic conductivity less than or equal to 1×10?6 times an ionic conductivity of the solid-state electrolyte.

Abstract: A panel is provided, including a first conductive pattern and a second conductive pattern. The first conductive pattern includes a first portion and a second portion; the second conductive pattern connects the first portion to the second portion, and an insulation pattern substantially covering a side surface of the second conductive pattern. The insulation pattern is formed by thermally treating a mask pattern of an insulation material. A horizontal distance between an outer side surface of the insulation pattern and an inner side surface adjacent to the second conductive pattern is less than 3 micrometers.

Abstract: Embodiments described herein provide a new layout editor tool allowing designers to concurrently edit various aspects of an electronic circuit layout, even at disparate hierarchical levels of the design. The new layout editor tool enables multiple electronic circuit designers to concurrently edit a layout a different hierarchical levels, by logically establishing editable child sub cell-level partitions within a parent layout-level partition, each of which representing various components of the same electronic circuit layout.

Abstract: A display panel includes a first substrate, a second substrate, at least one light-emitting diode, at least one reflective layer, and at least one first spacer layer. The first substrate has a filter layer. The second substrate is opposite to the first substrate. The light-emitting diode is disposed on the second substrate. The reflective layer is located on the first substrate and protrudes toward the second substrate. The first spacer layer is located between the first substrate and the second substrate. The first spacer layer has a first end and a second end, and the first end of the first spacer layer is located between a surface of the reflective layer adjacent to the second substrate and the second substrate.

Abstract: A system includes a plurality of servers in a server rack and a plurality of baseboard management controllers (BMCs), each associated with a respective server from the plurality of servers. The system further includes a rack management controller (RMC). A first BMC of a first server determines component types of hardware components in the first server, determines a quantity of each of the component types in the first server, determines a first weight information of the first server based on the component types and the quantity of each of the component types, and sends to the RMC the first weight information. The RMC determines a weight of other components in the server rack, and calculates a loaded rack weight of the server rack based on the first weight information and the weight of other components.

Abstract: A panel is provided, including a first conductive pattern and a second conductive pattern. The first conductive pattern includes a first portion and a second portion; the second conductive pattern connects the first portion to the second portion, and an insulation pattern substantially covering a side surface of the second conductive pattern. The insulation pattern is formed by thermally treating a mask pattern of an insulation material. A horizontal distance between an outer side surface of the insulation pattern and an inner side surface adjacent to the second conductive pattern is less than 3 micrometers.

Abstract: A method for manufacturing a panel is provided, including forming a first conductive pattern including a first portion and a second portion, forming a second conductive pattern connecting between the first portion and the second portion, and thermally treating a mask pattern of an insulation material to form an insulation pattern substantially covering a side surface of the second conductive pattern. A panel manufactured by using the foregoing method is also provided. A horizontal distance between an outer side surface of the insulation pattern and an inner side surface adjacent to the second conductive pattern is less than 3 micrometers.

Abstract: A baseboard management controller (BMC) of a system can receive a first serial output from a first server device and a second serial output from a second server device. The BMC can send the first serial output and the second serial output to a network interface controller (NIC) for transmission over a network to a computing device.

Abstract: A method for manufacturing a panel is provided, including forming a first conductive pattern including a first portion and a second portion, forming a second conductive pattern connecting between the first portion and the second portion, and thermally treating a mask pattern of an insulation material to form an insulation pattern substantially covering a side surface of the second conductive pattern. A panel manufactured by using the foregoing method is also provided. A horizontal distance between an outer side surface of the insulation pattern and an inner side surface adjacent to the second conductive pattern is less than 3 micrometers.

Abstract: A device substrate and a fabricating method thereof are provided. The device substrate includes a substrate and a patterned light-shielding layer. The patterned light-shielding layer having a plurality of pixel openings and a plurality of first exposure openings is disposed on the substrate, and an area and/or shape of one of the first exposure openings is different from an area and/or shape of one of the pixel openings.

Abstract: Disclosed are techniques for implementing electronic design layouts with symbolic representations. These techniques determine an abstraction scope of a layout circuit component in a layout of an electronic design by referencing a user input or one or more default settings of the abstraction mechanism and identify first data that are included in or associated with a schematic symbol for the layout circuit component by traversing data from a symbolic representation data source with reference to the abstraction scope with the layout editing mechanism. In addition, these techniques further generate a symbolic representation for the layout circuit component by reproducing at least some of the first data in the layout and perform one or more layout operations on the symbolic representation to improve the layout and to generate a result set for the one or more layout operations.

Abstract: A device substrate and a fabricating method thereof are provided. The device substrate includes a substrate and a patterned light-shielding layer. The patterned light-shielding layer having a plurality of pixel openings and a plurality of first exposure openings is disposed on the substrate, and an area and/or shape of one of the first exposure openings is different from an area and/or shape of one of the pixel openings.

Abstract: An exemplary method for making a light blocking plate includes the steps of providing a flat plate-like light pervious member; forming a plurality of spaced ceramic power layers on the light pervious member; forming a light blocking layer over the light pervious member and side faces of the ceramic power layers; forming an electromagnetic shielding layer over the light blocking layer; removing top portions of the ceramic power layers with remaining portions of the ceramic power layers thus exposed; and removing the remaining portions of the ceramic power layers.

Abstract: A device substrate and a fabricating method thereof are provided. The device substrate includes a substrate and a patterned light-shielding layer. The patterned light-shielding layer having a plurality of pixel openings and a plurality of first exposure openings is disposed on the substrate, and an area and/or shape of one of the first exposure openings is different from an area and/or shape of one of the pixel openings.