Patents by Inventor Kai Pei

Kai Pei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11558898
    Abstract: A random access method, a base station, an UE and a device with a storage function are disclosed. The random access method includes: the base station receiving a first message transmitted by the UE, the first message including a preamble message and a signal message; decoding the preamble message and the signal message respectively; if the decoding of preamble message is succeeded, but the decoding of signal message fails, the base station transmits a second message to the UE, and storing the signal message of decoding failure, the second message configured to request the UE to retransmit the signal message; receiving the third message transmitted by the UE, the third message including the signal message; using a chase combine mechanism to decode the third message according to the stored signal message in the first message. The present disclosure save time and improve the efficiency of random access.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: January 17, 2023
    Assignee: HUIZHOU TCL MOBILE COMMUNICATION CO., LTD.
    Inventors: Hua Qian, Jianxin Jia, Kai Kang, Zhenghang Zhu, Xuming Pei, Zhenyu Tang
  • Publication number: 20220374676
    Abstract: A computing method, suitable for computing a transformer model, include following steps. An input matrix corresponding to an input sequence of feature vectors is projected into a query matrix according to first learnable weights. The input matrix is projected into a value matrix according to second learnable weights. A factorized matrix is generated by an incomplete Cholesky factorization according to the query matrix and a transpose of the query matrix. An intermediate matrix is calculated according to a product between a transpose of the factorized matrix and the value matrix. An output matrix is calculated according to a product between the factorized matrix (H) and the intermediate matrix.
    Type: Application
    Filed: May 24, 2022
    Publication date: November 24, 2022
    Inventors: Tsu-Pei CHEN, Zheng-Yu WU, Kai-Fu TANG, Edward CHANG
  • Publication number: 20220359608
    Abstract: A display panel includes a first substrate, a second substrate, a light-emitting diode, a white insulation layer, and a first spacer layer. The first substrate has a filter layer and at least one black matrix. The second substrate is opposite to the first substrate. The light-emitting diode is disposed on the second substrate. The white insulation layer is located on the first substrate and protrudes toward the second substrate. The white insulation layer is overlapped with the filter layer and the black matrix along a first direction substantially perpendicular to the first substrate. The first spacer layer is disposed between the second substrate and the white insulation layer, and the first spacer layer is overlapped with the black matrix along the first direction.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Inventor: Kai PEI
  • Publication number: 20220342099
    Abstract: The present application provides a seafloor multi-wave seismic source including: a pressure chamber mechanism; a high-voltage pulse generator with four discharge pathways; a thrust mechanism with a thrust rod and a thrust head; four vibrators are evenly distributed around a periphery of the thrust head, and each vibrator is connected with one discharge pathway of the high-voltage pulse generator; a power supply unit to power the seismic source; and a processor, a memory and a program, wherein the program is stored in the memory and configured to be executed by the processor; and the program includes: pulse emission instructions generated by the processor based on user settings and received by the high-voltage pulse generator, for switching on four or any two of the four discharge pathways at the same time, to enable the corresponding vibrators to vibrate to excite seismic waves in compression wave mode or shear wave mode.
    Type: Application
    Filed: February 28, 2022
    Publication date: October 27, 2022
    Inventors: Yanliang PEI, Kai LIU, Mingming WEN, Chenguang LIU, Yifan HUANG, Liancheng ZHANG, Keping YAN, Baohua LIU
  • Patent number: 11477018
    Abstract: The disclosure provides a method, a device and a system for encrypting interactive data. In an aspect, the method includes: receiving a request for accessing a network from a terminal device, the request includes a device identifier of the terminal device; generating a random encryption code according to the device identifier; and feeding back the random encryption code to the terminal device so that the terminal device encrypts interactive data using the random encryption code after accessing the network. In another aspect, the method includes: transmitting a request for accessing a network to a gateway device, the request includes a device identifier of a terminal device; receiving a random encryption code fed back by the gateway device, the random encryption code is information for encrypting interactive data during the terminal device accessing the network; and encrypting interactive data with the random encryption code.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: October 18, 2022
    Assignee: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Kai Zhao, Lingfeng Xu, Hongyan Pei, Pan Ni
  • Patent number: 11430829
    Abstract: A display panel includes a first substrate, a second substrate, at least one light-emitting diode, at least one reflective layer, and at least one first spacer layer. The first substrate has a filter layer. The second substrate is opposite to the first substrate. The light-emitting diode is disposed on the second substrate. The reflective layer is located on the first substrate and protrudes toward the second substrate. The first spacer layer is located between the first substrate and the second substrate. The first spacer layer has a first end and a second end, and the first end of the first spacer layer is located between a surface of the reflective layer adjacent to the second substrate and the second substrate.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: August 30, 2022
    Assignee: AU OPTRONICS CORPORATION
    Inventor: Kai Pei
  • Patent number: 11347914
    Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include performing, using a processor, an electronic design process on a portion of an electronic design. Embodiments may also include automatically monitoring the electronic design process on a periodic basis using a pulse monitor to acquire one or more sampling results and storing the one or more sampling results. Embodiments may further include providing, during the electronic design process, the one or more sampling results to a graphical user interface.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: May 31, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wei-Cheng Chen, Yuan-Kai Pei, Yu-Chi Su
  • Publication number: 20220052374
    Abstract: A buffered negative electrode-electrolyte assembly includes: a porous negative electrode comprising a metal, a transition metal nitride, or a combination thereof; a solid-state electrolyte; and a buffer layer between the porous negative electrode and the solid-state electrolyte. The buffer layer comprising a buffer composition according to Formula (1) MmNnZzHhXx. The buffer composition has an electronic conductivity that is less than or equal to 1×10?2 times an electronic conductivity of the solid-state electrolyte, and the buffer composition has an ionic conductivity less than or equal to 1×10?6 times an ionic conductivity of the solid-state electrolyte.
    Type: Application
    Filed: January 8, 2021
    Publication date: February 17, 2022
    Inventors: Andrea Maurano, Srinath Chakravarthy, Ju Li, Ziqiang Wang, Yuming Chen, Kai Pei, Jennifer Lilia Marguerite Rupp
  • Patent number: 11023061
    Abstract: A panel is provided, including a first conductive pattern and a second conductive pattern. The first conductive pattern includes a first portion and a second portion; the second conductive pattern connects the first portion to the second portion, and an insulation pattern substantially covering a side surface of the second conductive pattern. The insulation pattern is formed by thermally treating a mask pattern of an insulation material. A horizontal distance between an outer side surface of the insulation pattern and an inner side surface adjacent to the second conductive pattern is less than 3 micrometers.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: June 1, 2021
    Assignee: AU OPTRONICS CORPORATION
    Inventor: Kai Pei
  • Patent number: 10922469
    Abstract: Embodiments described herein provide a new layout editor tool allowing designers to concurrently edit various aspects of an electronic circuit layout, even at disparate hierarchical levels of the design. The new layout editor tool enables multiple electronic circuit designers to concurrently edit a layout a different hierarchical levels, by logically establishing editable child sub cell-level partitions within a parent layout-level partition, each of which representing various components of the same electronic circuit layout.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: February 16, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yuan-Kai Pei, Gautam Kumar, Gerard Tarroux
  • Publication number: 20200365650
    Abstract: A display panel includes a first substrate, a second substrate, at least one light-emitting diode, at least one reflective layer, and at least one first spacer layer. The first substrate has a filter layer. The second substrate is opposite to the first substrate. The light-emitting diode is disposed on the second substrate. The reflective layer is located on the first substrate and protrudes toward the second substrate. The first spacer layer is located between the first substrate and the second substrate. The first spacer layer has a first end and a second end, and the first end of the first spacer layer is located between a surface of the reflective layer adjacent to the second substrate and the second substrate.
    Type: Application
    Filed: February 20, 2020
    Publication date: November 19, 2020
    Inventor: Kai PEI
  • Patent number: 10587935
    Abstract: A system includes a plurality of servers in a server rack and a plurality of baseboard management controllers (BMCs), each associated with a respective server from the plurality of servers. The system further includes a rack management controller (RMC). A first BMC of a first server determines component types of hardware components in the first server, determines a quantity of each of the component types in the first server, determines a first weight information of the first server based on the component types and the quantity of each of the component types, and sends to the RMC the first weight information. The RMC determines a weight of other components in the server rack, and calculates a loaded rack weight of the server rack based on the first weight information and the weight of other components.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: March 10, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Kai-Pei Chou, Chin-Tsai Yen, Ching-Chih Shih
  • Publication number: 20190369789
    Abstract: A panel is provided, including a first conductive pattern and a second conductive pattern. The first conductive pattern includes a first portion and a second portion; the second conductive pattern connects the first portion to the second portion, and an insulation pattern substantially covering a side surface of the second conductive pattern. The insulation pattern is formed by thermally treating a mask pattern of an insulation material. A horizontal distance between an outer side surface of the insulation pattern and an inner side surface adjacent to the second conductive pattern is less than 3 micrometers.
    Type: Application
    Filed: August 13, 2019
    Publication date: December 5, 2019
    Inventor: Kai PEI
  • Patent number: 10429976
    Abstract: A method for manufacturing a panel is provided, including forming a first conductive pattern including a first portion and a second portion, forming a second conductive pattern connecting between the first portion and the second portion, and thermally treating a mask pattern of an insulation material to form an insulation pattern substantially covering a side surface of the second conductive pattern. A panel manufactured by using the foregoing method is also provided. A horizontal distance between an outer side surface of the insulation pattern and an inner side surface adjacent to the second conductive pattern is less than 3 micrometers.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: October 1, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventor: Kai Pei
  • Patent number: 10127170
    Abstract: A baseboard management controller (BMC) of a system can receive a first serial output from a first server device and a second serial output from a second server device. The BMC can send the first serial output and the second serial output to a network interface controller (NIC) for transmission over a network to a computing device.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: November 13, 2018
    Assignee: QUANTA COMPUTER INC.
    Inventors: Te-Hsien Lai, Kai-Pei Chou
  • Publication number: 20180210589
    Abstract: A method for manufacturing a panel is provided, including forming a first conductive pattern including a first portion and a second portion, forming a second conductive pattern connecting between the first portion and the second portion, and thermally treating a mask pattern of an insulation material to form an insulation pattern substantially covering a side surface of the second conductive pattern. A panel manufactured by using the foregoing method is also provided. A horizontal distance between an outer side surface of the insulation pattern and an inner side surface adjacent to the second conductive pattern is less than 3 micrometers.
    Type: Application
    Filed: October 23, 2017
    Publication date: July 26, 2018
    Inventor: Kai PEI
  • Patent number: 10012905
    Abstract: A device substrate and a fabricating method thereof are provided. The device substrate includes a substrate and a patterned light-shielding layer. The patterned light-shielding layer having a plurality of pixel openings and a plurality of first exposure openings is disposed on the substrate, and an area and/or shape of one of the first exposure openings is different from an area and/or shape of one of the pixel openings.
    Type: Grant
    Filed: September 25, 2016
    Date of Patent: July 3, 2018
    Assignee: Au Optronics Corporations
    Inventor: Kai Pei
  • Patent number: 9779193
    Abstract: Disclosed are techniques for implementing electronic design layouts with symbolic representations. These techniques determine an abstraction scope of a layout circuit component in a layout of an electronic design by referencing a user input or one or more default settings of the abstraction mechanism and identify first data that are included in or associated with a schematic symbol for the layout circuit component by traversing data from a symbolic representation data source with reference to the abstraction scope with the layout editing mechanism. In addition, these techniques further generate a symbolic representation for the layout circuit component by reproducing at least some of the first data in the layout and perform one or more layout operations on the symbolic representation to improve the layout and to generate a result set for the one or more layout operations.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: October 3, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Arnold Ginetti, Yuan-Kai Pei, Yu-Chi Su
  • Patent number: 9581906
    Abstract: A device substrate and a fabricating method thereof are provided. The device substrate includes a substrate and a patterned light-shielding layer. The patterned light-shielding layer having a plurality of pixel openings and a plurality of first exposure openings is disposed on the substrate, and an area and/or shape of one of the first exposure openings is different from an area and/or shape of one of the pixel openings.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: February 28, 2017
    Assignee: Au Optronics Corporation
    Inventor: Kai Pei
  • Patent number: 9575215
    Abstract: An exemplary method for making a light blocking plate includes the steps of providing a flat plate-like light pervious member; forming a plurality of spaced ceramic power layers on the light pervious member; forming a light blocking layer over the light pervious member and side faces of the ceramic power layers; forming an electromagnetic shielding layer over the light blocking layer; removing top portions of the ceramic power layers with remaining portions of the ceramic power layers thus exposed; and removing the remaining portions of the ceramic power layers.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: February 21, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Shao-Kai Pei