Patents by Inventor Kai Pei
Kai Pei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12451516Abstract: A buffered negative electrode-electrolyte assembly includes: a porous negative electrode comprising a metal, a transition metal nitride, or a combination thereof; a solid-state electrolyte; and a buffer layer between the porous negative electrode and the solid-state electrolyte. The buffer layer comprising a buffer composition according to Formula (1) MmNnZzHhXx. The buffer composition has an electronic conductivity that is less than or equal to 1×10?2 times an electronic conductivity of the solid-state electrolyte, and the buffer composition has an ionic conductivity less than or equal to 1×10?6 times an ionic conductivity of the solid-state electrolyte.Type: GrantFiled: April 21, 2023Date of Patent: October 21, 2025Assignees: SAMSUNG ELECTRONICS CO., LTD., MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Andrea Maurano, Srinath Chakravarthy, Ju Li, Ziqiang Wang, Yuming Chen, Kai Pei, Jennifer Lilia Marguerite Rupp
-
Publication number: 20230361338Abstract: An electrochemical cell and a method of manufacturing the electrochemical cell are provided. The method includes: spraying a precursor solution on an anode, the precursor solution including a metal salt dissolved in a solvent and the anode being at a temperature of 250° C. or greater; reacting the metal salt on the anode to form a buffer layer; and attaching a solid-state electrolyte to the buffer layer.Type: ApplicationFiled: May 16, 2022Publication date: November 9, 2023Inventors: Andrea Maurano, Jesse John Hinricher, So Yeon Kim, Jennifer Lilia Marguerite Rupp, Ju Li, Yuntong Zhu, Hyunwon Chu, Zachary David Hood, Won Seok Chang, Kai Pei, Yimeng Huang, Srinath Chakravarthy, Ziqiang Wang
-
Publication number: 20230253616Abstract: A buffered negative electrode-electrolyte assembly includes: a porous negative electrode comprising a metal, a transition metal nitride, or a combination thereof; a solid-state electrolyte; and a buffer layer between the porous negative electrode and the solid-state electrolyte. The buffer layer comprising a buffer composition according to Formula (1) MmNnZzHhXx. The buffer composition has an electronic conductivity that is less than or equal to 1×10-2 times an electronic conductivity of the solid-state electrolyte, and the buffer composition has an ionic conductivity less than or equal to 1×10-6 times an ionic conductivity of the solid-state electrolyte.Type: ApplicationFiled: April 21, 2023Publication date: August 10, 2023Inventors: Andrea Maurano, Srinath Chakravarthy, Ju Li, Ziqiang Wang, Yuming Chen, Kai Pei, Jennifer Lilia Marguerite Rupp
-
Patent number: 11664529Abstract: A buffered negative electrode-electrolyte assembly includes: a porous negative electrode comprising a metal, a transition metal nitride, or a combination thereof; a solid-state electrolyte; and a buffer layer between the porous negative electrode and the solid-state electrolyte. The buffer layer comprising a buffer composition according to Formula (1) MmNnZzHhXx. The buffer composition has an electronic conductivity that is less than or equal to 1×10?2 times an electronic conductivity of the solid-state electrolyte, and the buffer composition has an ionic conductivity less than or equal to 1×10?6 times an ionic conductivity of the solid-state electrolyte.Type: GrantFiled: January 8, 2021Date of Patent: May 30, 2023Assignees: SAMSUNG ELECTRONICS CO., LTD., MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Andrea Maurano, Srinath Chakravarthy, Ju Li, Ziqiang Wang, Yuming Chen, Kai Pei, Jennifer Lilia Marguerite Rupp
-
Publication number: 20220359608Abstract: A display panel includes a first substrate, a second substrate, a light-emitting diode, a white insulation layer, and a first spacer layer. The first substrate has a filter layer and at least one black matrix. The second substrate is opposite to the first substrate. The light-emitting diode is disposed on the second substrate. The white insulation layer is located on the first substrate and protrudes toward the second substrate. The white insulation layer is overlapped with the filter layer and the black matrix along a first direction substantially perpendicular to the first substrate. The first spacer layer is disposed between the second substrate and the white insulation layer, and the first spacer layer is overlapped with the black matrix along the first direction.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Inventor: Kai PEI
-
Patent number: 11430829Abstract: A display panel includes a first substrate, a second substrate, at least one light-emitting diode, at least one reflective layer, and at least one first spacer layer. The first substrate has a filter layer. The second substrate is opposite to the first substrate. The light-emitting diode is disposed on the second substrate. The reflective layer is located on the first substrate and protrudes toward the second substrate. The first spacer layer is located between the first substrate and the second substrate. The first spacer layer has a first end and a second end, and the first end of the first spacer layer is located between a surface of the reflective layer adjacent to the second substrate and the second substrate.Type: GrantFiled: February 20, 2020Date of Patent: August 30, 2022Assignee: AU OPTRONICS CORPORATIONInventor: Kai Pei
-
Publication number: 20220052374Abstract: A buffered negative electrode-electrolyte assembly includes: a porous negative electrode comprising a metal, a transition metal nitride, or a combination thereof; a solid-state electrolyte; and a buffer layer between the porous negative electrode and the solid-state electrolyte. The buffer layer comprising a buffer composition according to Formula (1) MmNnZzHhXx. The buffer composition has an electronic conductivity that is less than or equal to 1×10?2 times an electronic conductivity of the solid-state electrolyte, and the buffer composition has an ionic conductivity less than or equal to 1×10?6 times an ionic conductivity of the solid-state electrolyte.Type: ApplicationFiled: January 8, 2021Publication date: February 17, 2022Inventors: Andrea Maurano, Srinath Chakravarthy, Ju Li, Ziqiang Wang, Yuming Chen, Kai Pei, Jennifer Lilia Marguerite Rupp
-
Patent number: 11023061Abstract: A panel is provided, including a first conductive pattern and a second conductive pattern. The first conductive pattern includes a first portion and a second portion; the second conductive pattern connects the first portion to the second portion, and an insulation pattern substantially covering a side surface of the second conductive pattern. The insulation pattern is formed by thermally treating a mask pattern of an insulation material. A horizontal distance between an outer side surface of the insulation pattern and an inner side surface adjacent to the second conductive pattern is less than 3 micrometers.Type: GrantFiled: August 13, 2019Date of Patent: June 1, 2021Assignee: AU OPTRONICS CORPORATIONInventor: Kai Pei
-
Publication number: 20200365650Abstract: A display panel includes a first substrate, a second substrate, at least one light-emitting diode, at least one reflective layer, and at least one first spacer layer. The first substrate has a filter layer. The second substrate is opposite to the first substrate. The light-emitting diode is disposed on the second substrate. The reflective layer is located on the first substrate and protrudes toward the second substrate. The first spacer layer is located between the first substrate and the second substrate. The first spacer layer has a first end and a second end, and the first end of the first spacer layer is located between a surface of the reflective layer adjacent to the second substrate and the second substrate.Type: ApplicationFiled: February 20, 2020Publication date: November 19, 2020Inventor: Kai PEI
-
Publication number: 20190369789Abstract: A panel is provided, including a first conductive pattern and a second conductive pattern. The first conductive pattern includes a first portion and a second portion; the second conductive pattern connects the first portion to the second portion, and an insulation pattern substantially covering a side surface of the second conductive pattern. The insulation pattern is formed by thermally treating a mask pattern of an insulation material. A horizontal distance between an outer side surface of the insulation pattern and an inner side surface adjacent to the second conductive pattern is less than 3 micrometers.Type: ApplicationFiled: August 13, 2019Publication date: December 5, 2019Inventor: Kai PEI
-
Patent number: 10429976Abstract: A method for manufacturing a panel is provided, including forming a first conductive pattern including a first portion and a second portion, forming a second conductive pattern connecting between the first portion and the second portion, and thermally treating a mask pattern of an insulation material to form an insulation pattern substantially covering a side surface of the second conductive pattern. A panel manufactured by using the foregoing method is also provided. A horizontal distance between an outer side surface of the insulation pattern and an inner side surface adjacent to the second conductive pattern is less than 3 micrometers.Type: GrantFiled: October 23, 2017Date of Patent: October 1, 2019Assignee: AU OPTRONICS CORPORATIONInventor: Kai Pei
-
Publication number: 20180210589Abstract: A method for manufacturing a panel is provided, including forming a first conductive pattern including a first portion and a second portion, forming a second conductive pattern connecting between the first portion and the second portion, and thermally treating a mask pattern of an insulation material to form an insulation pattern substantially covering a side surface of the second conductive pattern. A panel manufactured by using the foregoing method is also provided. A horizontal distance between an outer side surface of the insulation pattern and an inner side surface adjacent to the second conductive pattern is less than 3 micrometers.Type: ApplicationFiled: October 23, 2017Publication date: July 26, 2018Inventor: Kai PEI
-
Patent number: 10012905Abstract: A device substrate and a fabricating method thereof are provided. The device substrate includes a substrate and a patterned light-shielding layer. The patterned light-shielding layer having a plurality of pixel openings and a plurality of first exposure openings is disposed on the substrate, and an area and/or shape of one of the first exposure openings is different from an area and/or shape of one of the pixel openings.Type: GrantFiled: September 25, 2016Date of Patent: July 3, 2018Assignee: Au Optronics CorporationsInventor: Kai Pei
-
Patent number: 9581906Abstract: A device substrate and a fabricating method thereof are provided. The device substrate includes a substrate and a patterned light-shielding layer. The patterned light-shielding layer having a plurality of pixel openings and a plurality of first exposure openings is disposed on the substrate, and an area and/or shape of one of the first exposure openings is different from an area and/or shape of one of the pixel openings.Type: GrantFiled: June 27, 2014Date of Patent: February 28, 2017Assignee: Au Optronics CorporationInventor: Kai Pei
-
Publication number: 20170010536Abstract: A device substrate and a fabricating method thereof are provided. The device substrate includes a substrate and a patterned light-shielding layer. The patterned light-shielding layer having a plurality of pixel openings and a plurality of first exposure openings is disposed on the substrate, and an area and/or shape of one of the first exposure openings is different from an area and/or shape of one of the pixel openings.Type: ApplicationFiled: September 25, 2016Publication date: January 12, 2017Applicant: Au Optronics CorporationInventor: Kai Pei
-
Publication number: 20150293279Abstract: A device substrate and a fabricating method thereof are provided. The device substrate includes a substrate and a patterned light-shielding layer. The patterned light-shielding layer having a plurality of pixel openings and a plurality of first exposure openings is disposed on the substrate, and an area and/or shape of one of the first exposure openings is different from an area and/or shape of one of the pixel openings.Type: ApplicationFiled: June 27, 2014Publication date: October 15, 2015Inventor: Kai Pei
-
Patent number: 8570742Abstract: An enclosure includes a case and a cover. The case includes a heat generating device and a bracket mounted therein. The bracket defines an engaging hole. A heat dissipating module is located in the engaging hole and contacts the heat generating device. The cover includes a number of mounting poles pivotally mounted thereon. The cover is mounted on the case. The mounting poles are engaged on the bracket to enclose the heat dissipating module.Type: GrantFiled: June 3, 2011Date of Patent: October 29, 2013Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Chin-Wen Yeh, Yang Xiao, Kai Pei
-
Patent number: 8550524Abstract: A pick-up device includes an sucking member, a blocking member, a grasping assembly, a restricting member and a covering member. The sucking member is adapted to utilize a vacuum to adhere to the surface of an electronic component and defines a through hole. The blocking member is secured to the sucking member and includes a blocking block. The finger-grasping assembly is slidably mounted to blocking member. The restricting member is movably mounted to the grasping assembly and movable relative to the sucking member. The restricting member includes two restricting portions. The covering member is secured to the restricting member by a first resilient member. The grasping assembly is operable to bias the restricting member and the covering member to move relative to the sucking member, the two restricting portions are engaged with the blocking block, and the covering member seals the through hole.Type: GrantFiled: March 8, 2012Date of Patent: October 8, 2013Assignees: Hong Fu Jin Precision Industry (WuHan) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Chin-Wen Yeh, Yang Xiao, Kai Pei
-
Publication number: 20130118007Abstract: A fixture is for installing a hard disk to a hard disk cage in a computer the fixture. The fixture includes a holding portion and a supporting portion connecting with the holding portion. The supporting portion includes a main plate and a side plate bending from the main plate. A slot is defined between the main plate and the side plate, for receiving the hard disk cage and retaining the fixture to the hard disk cage.Type: ApplicationFiled: October 1, 2012Publication date: May 16, 2013Inventors: CHIN-WEN YEH, ZHI-JIAN PENG, YANG XIAO, KAI PEI
-
Publication number: 20120326458Abstract: A pick-up device includes an sucking member, a blocking member, a grasping assembly, a restricting member and a covering member. The sucking member is adapted to utilize a vacuum to adhere to the surface of an electronic component and defines a through hole. The blocking member is secured to the sucking member and includes a blocking block. The finger-grasping assembly is slidably mounted to blocking member. The restricting member is movably mounted to the grasping assembly and movable relative to the sucking member. The restricting member includes two restricting portions. The covering member is secured to the restricting member by a first resilient member. The grasping assembly is operable to bias the restricting member and the covering member to move relative to the sucking member, the two restricting portions are engaged with the blocking block, and the covering member seals the through hole.Type: ApplicationFiled: March 8, 2012Publication date: December 27, 2012Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (WUHAN) CO., LTD.Inventors: CHIN-WEN YEH, YANG XIAO, KAI PEI