Abstract: A method for detecting defects on a wafer including the steps of obtaining a reference image of a chip pattern formed on a reference wafer, using a computer algorithm to analyze the reference image to produce a division map for the chip pattern; setting respective thresholds for divisions of the division map, obtaining a comparison data between a test image of the chip pattern formed on a test wafer and the reference image, using the division map and the thresholds to examine the comparison data to identify a defect in the test image.

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

Abstract: A method of decreasing height differences of STIs includes providing a substrate comprising a peripheral circuit region. The peripheral circuit region includes a P-type transistor region and an N-type transistor region. A first STI and a third STI are respectively disposed within the N-type transistor region and the P-type transistor region. Later, a first mask is formed to cover the N-type transistor region. Then, an N-type well is formed in the P-type transistor region and part of the third STI is removed by taking the first mask as a mask. Next, the first mask is removed. After that, a second mask is formed to cover the P-type transistor region. Subsequently, a P-type well is formed in the N-type transistor region and part of the first STI is removed by taking the second mask as a mask. Finally, the second mask is removed.

Abstract: A method of decreasing height differences of STIs includes providing a substrate comprising a peripheral circuit region. The peripheral circuit region includes a P-type transistor region and an N-type transistor region. A first STI and a third STI are respectively disposed within the N-type transistor region and the P-type transistor region. Later, a first mask is formed to cover the N-type transistor region. Then, an N-type well is formed in the P-type transistor region and part of the third STI is removed by taking the first mask as a mask. Next, the first mask is removed. After that, a second mask is formed to cover the P-type transistor region. Subsequently, a P-type well is formed in the N-type transistor region and part of the first STI is removed by taking the second mask as a mask. Finally, the second mask is removed.

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

Abstract: A defect inspection method for a wafer is provided. The wafer comprises a component pattern. The method comprises the following steps: providing a defect inspection apparatus for inspecting the defects on the wafer to obtain a defect distribution map; providing a photo mask, wherein the photo mask comprises a exposure pattern corresponding to the component pattern; and comparing the defect distribution map with the exposure pattern and dividing the defects in the defect distribution map into a first killer defect group and a first non-killer defect group according to their corresponding locations in the exposure pattern. In addition, a wafer defect inspection system applying the same method is also provided.

Abstract: A defect inspection method for a wafer is provided. The wafer comprises a component pattern. The method comprises the following steps: providing a defect inspection apparatus for inspecting the defects on the wafer to obtain a defect distribution map; providing a photo mask, wherein the photo mask comprises a exposure pattern corresponding to the component pattern; and comparing the defect distribution map with the exposure pattern and dividing the defects in the defect distribution map into a first killer defect group and a first non-killer defect group according to their corresponding locations in the exposure pattern. In addition, a wafer defect inspection system applying the same method is also provided.

Abstract: A sampling inspection method is provided. The sampling inspection method is adapted for a multi-product production line including a plurality of tools. The sampling inspection method includes the steps of: providing a tool record, which records a sampling data of each of the tools; then checking each sampling data recorded in the tool record, and finding out at least one unsampled tool from the tools; then defining a plurality of product lots as being performed with process operations by at least one of the at least one unsampled tool; and determining at least one of the product lots for performing a sampling inspection.

Abstract: A sampling inspection method is provided. The sampling inspection method is adapted for a multi-product production line including a plurality of tools. The sampling inspection method includes the steps of: providing a tool record, which records a sampling data of each of the tools; then checking each sampling data recorded in the tool record, and finding out at least one unsampled tool from the tools; then defining a plurality of product lots as being performed with process operations by at least one of the at least one unsampled tool; and determining at least one of the product lots for performing a sampling inspection.

Abstract: A method of removing a photoresist layer is provided. An ion implantation process has been performed on the photoresist layer to transform a surface of the photoresist layer to a crust and a soft photoresist layer remains within the crust. The method includes performing a first removing step to remove the crust, such that the soft photoresist layer is exposed. Thereafter, a second removing step is performed to remove the soft photoresist layer. The first and the second removing steps are performed in difference chambers, and a temperature for performing the first removing step is lower than that for performing the second removing step and lower than a gasification temperature of a solvent in the soft photoresist layer.