Patents by Inventor Kai-Po Shang

Kai-Po Shang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12002752
    Abstract: The present disclosure provides a method for manufacturing a fuse component having a three-dimensional (3D) structure. The method includes providing an active region, forming a first recess region and a second recess region in the active region, disposing a fuse dielectric material in the first recess region and the second recess region, and filling the first recess region and the second recess region with a gate metal material.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: June 4, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Kai-Po Shang, Jui-Hsiu Jao
  • Patent number: 11916015
    Abstract: A fuse component, a semiconductor device, and a method of manufacturing a fuse component are provided. The fuse component includes an active region having a surface, a fuse dielectric layer extending from the surface of the active region into the active region, and a gate metal layer surrounded by the fuse dielectric layer.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: February 27, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Kai-Po Shang, Jui-Hsiu Jao
  • Publication number: 20230178482
    Abstract: A fuse component and a semiconductor device and a semiconductor device having the fuse component are provided. The fuse component includes an active region having a surface, a first fuse dielectric layer extending from the surface of the active region into the active region, a first gate metal layer surrounded by the first fuse dielectric layer, a second fuse dielectric layer extending from the surface of the active region into the active region, and a second gate metal layer surrounded by the second fuse dielectric layer. The first gate metal layer is electrically connected with the second gate metal layer.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 8, 2023
    Inventors: KAI-PO SHANG, JUI-HSIU JAO
  • Publication number: 20230178481
    Abstract: The present disclosure provides a method for manufacturing a fuse component having a three-dimensional (3D) structure. The method includes providing an active region, forming a first recess region and a second recess region in the active region, disposing a fuse dielectric material in the first recess region and the second recess region, and filling the first recess region and the second recess region with a gate metal material.
    Type: Application
    Filed: December 3, 2021
    Publication date: June 8, 2023
    Inventors: KAI-PO SHANG, JUI-HSIU JAO
  • Publication number: 20230125837
    Abstract: A fuse component, a semiconductor device, and a method of manufacturing a fuse component are provided. The fuse component includes an active region having a surface, a fuse dielectric layer extending from the surface of the active region into the active region, and a gate metal layer surrounded by the fuse dielectric layer.
    Type: Application
    Filed: October 26, 2021
    Publication date: April 27, 2023
    Inventors: KAI-PO SHANG, JUI-HSIU JAO
  • Publication number: 20230130975
    Abstract: A semiconductor device with a fuse component is provided. The semiconductor device includes a substrate having an active region; a fuse dielectric layer disposed in the active region; and a gate metal layer disposed in the active region and surrounded by the fuse dielectric layer. The he gate metal layer is configured to receive a voltage to change a resistivity between the gate metal layer and the active region.
    Type: Application
    Filed: October 22, 2021
    Publication date: April 27, 2023
    Inventors: KAI-PO SHANG, JUI-HSIU JAO
  • Patent number: 10756693
    Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a capacitor array, a decoder circuit, and an integrated circuit. The capacitor array includes a plurality of capacitor units. The decoder circuit is coupled to the capacitor array. The integrated circuit is coupled to the decoder circuit. The decoder circuit is configured to conduct part of the plurality of capacitor units, and to un-conduct part of the plurality of capacitor units, so as to adjust a capacitance value coupled to the integrated circuit.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: August 25, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Kai-Po Shang, Jui-Hsiu Jao