Abstract: A data processing system includes a first wafer comprising a plurality of first chips, and kerf and crack-stop structures around perimeters of the first chips, and a second wafer comprising a plurality second chips, a plurality of interconnect structures through a connection zone between the second chips, and a plurality of thru silicon vias, wherein the first wafer and the second wafer are bonded face-to-face such that the interconnect structures of the second wafer electrically connect adjacent chip sites of the first wafer and where a pitch of the chips on the first and second wafer are equal.

Abstract: A data processing system includes a first wafer comprising a plurality of first chips, and kerf and crack-stop structures around perimeters of the first chips, and a second wafer comprising a plurality second chips, a plurality of interconnect structures through a connection zone between the second chips, and a plurality of thru silicon vias, wherein the first wafer and the second wafer are bonded face-to-face such that the interconnect structures of the second wafer electrically connect adjacent chip sites of the first wafer and where a pitch of the chips on the first and second wafer are equal.

Abstract: A portable computing system includes a portable computing device consisting essentially of a logical processor, a memory in communication with the logical processor with operating system software, a high speed, secure wireless communication module in communication with the logical processor, an integrated power source suitable to provide all power needs of the portable computing device and an integrated electric power generation mechanism in communication with the integrated power source to recharge the integrated power source. In addition a visual display is provided that has a power supply separate from the integrated power source of the portable computing device and a complementary wireless communication module, the portable visual display in communication with the high speed, secure wireless communication module through the complementary wireless communication module. The portable computing device and the visual display do not share a physical connection.

Abstract: A video processing method and system for generating a foveated video display with sections having different resolutions uses a network channel for communicating video images having video sections of different resolutions, and includes a video transmission system for processing and transmitting the received video images over the network channel. The system assigns a larger portion of the network channel's bandwidth to a video section with higher resolution. Further, the system includes a video receiving system for receiving and seamlessly combining the first and second video sections of different resolutions to form an output video image on a display device, and a control unit for sending one or more video control parameters to the video transmission system to control capturing, transmitting and processing of the video images.

Abstract: A video processing method and system for generating a foveated video display with sections having different resolutions uses a network channel for communicating video images having video sections of different resolutions, and includes a video transmission system for processing and transmitting the received video images over the network channel. The system assigns a larger portion of the network channel's bandwidth to a video section with higher resolution. Further, the system includes a video receiving system for receiving and seamlessly combining the first and second video sections of different resolutions to form an output video image on a display device, and a control unit for sending one or more video control parameters to the video transmission system to control capturing, transmitting and processing of the video images.

Abstract: A video processing method and system for generating a foveated video display with sections having different resolutions uses a network channel for communicating video images having video sections of different resolutions, and includes a video transmission system for processing and transmitting the received video images over the network channel. The system assigns a larger portion of the network channel's bandwidth to a video section with higher resolution. Further, the system includes a video receiving system for receiving and seamlessly combining the first and second video sections of different resolutions to form an output video image on a display device, and a control unit for sending one or more video control parameters to the video transmission system to control capturing, transmitting and processing of the video images.

Abstract: Disclosed is an image display device to secure uniformity of a screen without luminance unevenness by reducing the number of signal lines and enhancing accuracy in voltages to be applied to respective pixels. In an interval after a scan line Gn+2 is set to selection potential until the scan line Gn+2 is set to non-selection potential, a first display signal having first electric potential to be given to a pixel electrode A is supplied to a signal line, whereby the pixel electrode A and a pixel electrode B are provided with the first electric potential. In addition, after the scan line Gn+2 is set to the non-selection potential, a second display signal having second electric potential to be given to the pixel electrode B is supplied to the signal line, whereby the pixel electrode B is provided with the second electric potential.

Abstract: A video processing method and system for generating a foveated video display with sections having different resolutions uses a network channel for communicating video images having video sections of different resolutions, and includes a video transmission system for processing and transmitting the received video images over the network channel. The system assigns a larger portion of the network channel's bandwidth to a video section with higher resolution. Further, the system includes a video receiving system for receiving and seamlessly combining the first and second video sections of different resolutions to form an output video image on a display device, and a control unit for sending one or more video control parameters to the video transmission system to control capturing, transmitting and processing of the video images.

Abstract: A liquid crystal display includes a first TFT for controlling a supply of a display signal to a pixel electrode, a second TFT connected to the first TFT, and a third TFT connected to a data line. The third TFT controls the supply of a display signal to the pixel electrode. The second and third TFTs are connected to a gate line Gn+1, and the first TFT is connected to a gate line Gn+2.

Abstract: A high-frequency ignition system has a waveguide and a high-frequency amplifier. In this context, the high-frequency amplifier is situated at a first end of the waveguide. An ignition gap is situated at a second end of the waveguide. Additionally provided is a positive-feedback element, by which the frequency of the high-frequency amplifier is adapted to the load conditions of the waveguide and the ignition gap.

Abstract: When run on high pixel density monitors, software applications, which are written to be legible at all resolutions benefit greatly from the high pixel density. Other applications, especially those containing resources whose dimensions and placement are described in terms of numbers of pixels (e.g., a bitmap, text), may have reduced legibility. A method is described which facilitates legibility of both classes of software applications when run on high pixel density monitors.

Abstract: Disclosed is an image display device to secure uniformity of a screen without luminance unevenness by reducing the number of signal lines and enhancing accuracy in voltages to be applied to respective pixels. In an interval after a scan line Gn+2 is set to selection potential until the scan line Gn+2 is set to non-selection potential, a first display signal having first electric potential to be given to a pixel electrode A is supplied to a signal line, whereby the pixel electrode A and a pixel electrode B are provided with the first electric potential. In addition, after the scan line Gn+2 is set to the non-selection potential, a second display signal having second electric potential to be given to the pixel electrode B is supplied to the signal line, whereby the pixel electrode B is provided with the second electric potential.

Abstract: Proposed is a high-frequency ignition system, which has a waveguide (1) and a high-frequency amplifier (2). In this context, the high-frequency amplifier (2) is situated at a first end of the waveguide (1). An ignition gap (3) is situated at a second end of the waveguide (1). Additionally provided is a positive-feedback element (10), by which the frequency of the high-frequency amplifier (2) is adapted to the load conditions of the waveguide (1) and the ignition gap (3).

Abstract: A liquid crystal display includes a first TFT for controlling a supply of a display signal to a pixel electrode, a second TFT connected to the first TFT, and a third TFT connected to a data line. The third TFT controls the supply of a display signal to the pixel electrode. The second and third TFTs are connected to a gate line Gn+1, and the first TFT is connected to a gate line Gn+2.

Abstract: The circuit device has a plurality of cascaded stages. Each cascaded stage includes several partial stages and has at most two capacitors (C.sub.n1, C.sub.nB) and at most seven transistors (T.sub.n1, T.sub.n2, T.sub.n3, T.sub.n4, T.sub.n5, T.sub.n6, T.sub.n7). The circuit device includes a device for controlling the cascaded stages with four periodic clock signals (.PHI..sub.1, .PHI..sub.2, .PHI..sub.3, .sub.101 .sub.4) phase-shifted about 90.degree. relative to each other such that each of the cascaded stages is controlled by a respective assigned one of four predetermined sets of two of the four periodic clock signals and the same one of the four predetermined set repeats every fifth cascaded stage. Each cascaded stage includes an output stage (12, 12') including a bootstrap-capacitor (C.sub.nB) and three transistors (T.sub.n5, T.sub.n6, T.sub.n7) electrically connected to the bootstrap-capacitor (C.sub.nB); and a charging and discharging stage (11) for the bootstrap-capacitor (C.sub.nB).