Patents by Inventor Kai Shih

Kai Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250113504
    Abstract: Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 3, 2025
    Inventors: Wei Kai SHIH, Kuo-Liang WANG
  • Patent number: 12261363
    Abstract: A communication device includes a dielectric substrate, an antenna layer, a metamaterial layer, a first absorber element, a second absorber element, and a third absorber element. The dielectric substrate has a first surface and a second surface which are opposite to each other. The antenna layer is disposed on the first surface of the dielectric substrate. The metamaterial layer is adjacent to the antenna layer. The antenna layer and the metamaterial layer are both positioned between the first absorber element and the second absorber element. The third absorber element is disposed on the second surface of the dielectric substrate.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: March 25, 2025
    Assignee: WISTRON NEWEB CORP.
    Inventors: Jia-Hung Su, Kai Shih, Cheng-Geng Jan
  • Publication number: 20250015499
    Abstract: An antenna structure and an electronic device are provided. The electronic device includes a housing and an antenna structure disposed in the housing. The antenna structure includes a carrier having a first carrying part and a second carrying part connected to each other, a switching circuit, a first radiating element, and a second radiating element. A thickness of the first carrying part is greater than a thickness of the second carrying part. The second carrying part includes a circuit layer and a ground layer respectively formed on opposite surfaces of the second carrying part. The switching circuit is located on the circuit layer. The first radiating element and the second radiating element are disposed on the carrier and respectively electrically connected to a feed element and the switching circuit. The second radiating element and the first radiating element are apart from and couple with each other.
    Type: Application
    Filed: June 25, 2024
    Publication date: January 9, 2025
    Inventors: WEN-PIN HO, SHIH-KAI HSU, CHING-WEN CHEN, KAI SHIH
  • Patent number: 12191347
    Abstract: Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: January 7, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Kai Shih, Kuo-Liang Wang
  • Patent number: 12166009
    Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: December 10, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tang-Yuan Chen, Meng-Kai Shih, Teck-Chong Lee, Shin-Luh Tarng, Chih-Pin Hung
  • Publication number: 20240312910
    Abstract: One of the semiconductor devices includes a semiconductor substrate, a passivation layer and a conductive pattern. The semiconductor substrate includes a conductive pad thereover. The passivation layer over the semiconductor substrate. The conductive pattern is penetrating through the passivation layer and electrically connected to the conductive pad, wherein a sidewall of the conductive pattern interfacing with the passivation layer and the conductive pad has at least one turning point.
    Type: Application
    Filed: May 27, 2024
    Publication date: September 19, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wei-Kai Shih
  • Patent number: 12009296
    Abstract: Semiconductor device and method of forming the same are disclosed. One of the semiconductor devices includes a semiconductor substrate, a passivation layer and a conductive pattern. The semiconductor substrate includes a conductive pad thereover. The passivation layer over the semiconductor substrate. The conductive pattern is penetrating through the passivation layer and electrically connected to the conductive pad, wherein a sidewall of the conductive pattern has at least one turning point.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wei-Kai Shih
  • Publication number: 20240105815
    Abstract: A semiconductor structure and method of manufacture is provided. In some embodiments, a semiconductor structure includes a semiconductor layer, a first isolation structure in the semiconductor layer, a first gate structure adjacent a first side of the first isolation structure, a first source/drain region adjacent a second side of the first isolation structure, a second source/drain region adjacent the first gate structure, and a first conductive field plate at least partially embedded in the first isolation structure.
    Type: Application
    Filed: March 27, 2023
    Publication date: March 28, 2024
    Inventors: Chin-Yi HUANG, Shih Chan WEI, Wei Kai SHIH
  • Publication number: 20230411349
    Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.
    Type: Application
    Filed: August 29, 2023
    Publication date: December 21, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tang-Yuan CHEN, Meng-Kai SHIH, Teck-Chong LEE, Shin-Luh TARNG, Chih-Pin HUNG
  • Publication number: 20230387187
    Abstract: Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Inventors: Wei Kai SHIH, Kuo-Liang WANG
  • Publication number: 20230359796
    Abstract: A system and method for performing circuit design analysis obtains a circuit design comprising cells. The cells are associated with cell types. Aging parameters of a core analytical model are determined for each of the cell types in the circuit design to generate a calibrated analytical model. Aging effects for the cells are determined based on the calibrated analytical model and target stress conditions. An aged timing model is determined for the cell types based on the aging effects, an unaged timing model, and the target stress conditions.
    Type: Application
    Filed: December 7, 2022
    Publication date: November 9, 2023
    Inventors: Wei-Kai SHIH, Hsien-Han CHENG, Li DING
  • Publication number: 20230318193
    Abstract: A communication device includes a dielectric substrate, an antenna layer, a metamaterial layer, a first absorber element, a second absorber element, and a third absorber element. The dielectric substrate has a first surface and a second surface which are opposite to each other. The antenna layer is disposed on the first surface of the dielectric substrate. The metamaterial layer is adjacent to the antenna layer. The antenna layer and the metamaterial layer are both positioned between the first absorber element and the second absorber element. The third absorber element is disposed on the second surface of the dielectric substrate.
    Type: Application
    Filed: February 10, 2023
    Publication date: October 5, 2023
    Inventors: Jia-Hung SU, Kai SHIH, Cheng-Geng JAN
  • Patent number: 11776991
    Abstract: Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Kai Shih, Kuo-Liang Wang
  • Patent number: 11742324
    Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: August 29, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tang-Yuan Chen, Meng-Kai Shih, Teck-Chong Lee, Shin-Luh Tarng, Chih-Pin Hung
  • Publication number: 20230063261
    Abstract: Semiconductor device and method of forming the same are disclosed. One of the semiconductor devices includes a semiconductor substrate, a passivation layer and a conductive pattern. The semiconductor substrate includes a conductive pad thereover. The passivation layer over the semiconductor substrate. The conductive pattern is penetrating through the passivation layer and electrically connected to the conductive pad, wherein a sidewall of the conductive pattern has at least one turning point.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wei-Kai Shih
  • Publication number: 20230011464
    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, an intermediate layer and at least one through via. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The through via extends through the upper conductive structure, the intermediate layer and the lower conductive structure.
    Type: Application
    Filed: September 13, 2022
    Publication date: January 12, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Meng-Kai SHIH, Wei-Hong LAI, Wei Chu SUN
  • Patent number: 11375124
    Abstract: An optical measurement equipment includes an adjustment apparatus and at least two image capturing devices. The image capturing devices have a depth-of-field and attached to the adjustment apparatus. The image capturing devices are adjusted by the adjustment apparatus such that a portion to be measured of a workpiece is located within the depth-of-field of the image capturing devices.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: June 28, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Han Wang, Ian Hu, Meng-Kai Shih, Hsuan Yu Chen
  • Publication number: 20220085145
    Abstract: Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.
    Type: Application
    Filed: October 15, 2021
    Publication date: March 17, 2022
    Inventors: Wei Kai SHIH, Kuo-Liang WANG
  • Patent number: 11217502
    Abstract: A semiconductor device package includes a substrate, an electronic component disposed on the substrate, a supporting structure disposed on the substrate and surrounding the electronic component, and a heat spreading structure disposed on the supporting structure. A length of the supporting structure and a length of the heat spreading structure are greater than a length of the substrate.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: January 4, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ian Hu, Meng-Kai Shih, Chih-Pin Hung
  • Patent number: 11164935
    Abstract: Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Kai Shih, Kuo-Liang Wang