Abstract: A memory circuit includes a memory cell and a source line transistor. The memory cell includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The second transistor and the third transistor form an inverter electrically connected to a drain of the first transistor. The inverter is configured to store two states with different applied voltages. The fourth transistor is electrically connected to a node of the inverter. The source line transistor is electrically connected to the fourth transistor.

Abstract: A method includes forming a first transistor, a second transistor, a third transistor, and a fourth transistor over a substrate, wherein at least the second and third transistors include ferroelectric materials; forming an interlayer dielectric (ILD) layer over the first to fourth transistors; forming a first metal line over the ILD layer to interconnect drains of the second and third transistors and a gate of the fourth transistor; forming a second metal line over the ILD layer to interconnect a drain of the first transistor and gates of the second and third transistors; forming a write word line over the ILD layer and electrically connected to a gate of the first transistor but electrically isolated from the fourth transistor; forming a word line over the ILD layer and electrically connected to a source of the first transistor; and forming a bit line electrically connected to the fourth transistor.

Abstract: A memory circuit includes a memory cell and a source line transistor. The memory cell includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The second transistor and the third transistor form an inverter electrically connected to a drain of the first transistor. The inverter is configured to store two states with different applied voltages. The fourth transistor is electrically connected to a node of the inverter. The source line transistor is electrically connected to the fourth transistor.

Abstract: A field-effect transistor structure having two-dimensional transition metal dichalcogenides includes a substrate, a source/drain structure, a two-dimensional (2D) channel layer, and a gate layer. The source/drain structure is disposed on the substrate and has a surface higher than a surface of the substrate. The 2D channel layer is disposed on the source and the drain and covers the space between the source and the drain. The gate layer is disposed between the source and the drain and covers the 2D channel layer. The field-effect transistor having two-dimensional transition metal dichalcogenides is a planar field-effect transistor or a fin field-effect transistor.

Abstract: A field-effect transistor structure having two-dimensional transition metal dichalcogenides includes a substrate, a source/drain structure, a two-dimensional (2D) channel layer, and a gate layer. The source/drain structure is disposed on the substrate and has a surface higher than a surface of the substrate. The 2D channel layer is disposed on the source and the drain and covers the space between the source and the drain. The gate layer is disposed between the source and the drain and covers the 2D channel layer. The field-effect transistor having two-dimensional transition metal dichalcogenides is a planar field-effect transistor or a fin field-effect transistor.

Abstract: A tunneling magnetoresistance device with high magnetoimpedance effect, a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer which is located between the first ferromagnetic layer and the second ferromagnetic layer. Wherein an alternating current is applied to the tunneling magnetoresistance device, the tunneling magnetoresistance device has at least 100% variation of real components between an applied first alternating frequency and an applied second alternating frequency, at least 25% variation of imaginary components below the first alternating frequency, and at least 8.5% variation of magneto capacitance (MC) ratio which are generated along the magnetization direction.

Abstract: A tunneling magnetoresistance device with high magnetoimpedance effect, comprising: a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer which is located between the first ferromagnetic layer and the second ferromagnetic layer. Wherein an alternating current is applied to the tunneling magnetoresistance device, the tunneling magnetoresistance device has at least 100% variation of real components between an applied first alternating frequency and an applied second alternating frequency, at least 25% variation of imaginary components below the first alternating frequency, and at least 8.5% variation of magneto capacitance (MC) ratio which are generated along the magnetization direction.