Patents by Inventor Kai-Shiung Hsu
Kai-Shiung Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967522Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.Type: GrantFiled: April 25, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-Nan Lin, Chia-Yu Wu, Kai-Shiung Hsu, Ding-I Liu
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Publication number: 20230377955Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.Type: ApplicationFiled: July 28, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Jen CHEN, Kai-Shiung Hsu, Ding-I Liu, Jyh-nan Lin
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Publication number: 20230142009Abstract: Contamination from outgassing during a deposition process is addressed by a series of equipment enhancements, including throttle valves, a dual air curtain, and a residual gas analysis (RGA) monitor. The dual air curtain can be configured to flow a first gas during wafer processing and a second gas during wafer unloading, to re-direct and capture outgassed species. The dual air curtain and the throttle valves can be programmed in an automated feedback control system that utilizes data from the RGA monitor.Type: ApplicationFiled: June 9, 2022Publication date: May 11, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jia-Wei XU, Yin-Bin TSENG, Kai-Shiung HSU, Chun-Sheng WU
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Publication number: 20220333236Abstract: The present disclosure describes a semiconductor device manufacturing apparatus and a method for handling contamination in the semiconductor device manufacturing apparatus. The semiconductor device manufacturing apparatus can include a deposition apparatus and a processor. The deposition apparatus can include a chamber, a detection module configured to detect impurities in the chamber, and a gas scrubbing device configured to remove the impurities. The processor can be configured to receive, from the detection module, an impurity characteristic associated with the impurities; compare the impurity characteristic to a baseline characteristic; and instruct the gas scrubbing device to supply a decontamination gas in the chamber based on the comparison of the impurity characteristic to the baseline characteristic.Type: ApplicationFiled: April 16, 2021Publication date: October 20, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jia-Wei XU, Ding-I Liu, Kai-Shiung Hsu, Yin-Bin Tseng
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Publication number: 20220262677Abstract: In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.Type: ApplicationFiled: May 2, 2022Publication date: August 18, 2022Inventors: Hsiao-Min CHEN, Jyh-Nan LIN, Kai-Shiung HSU, Ding-I LIU
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Publication number: 20220254679Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.Type: ApplicationFiled: April 25, 2022Publication date: August 11, 2022Inventors: Jyh-Nan Lin, Chia-Yu Wu, Kai-Shiung Hsu, Ding-I Liu
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Publication number: 20220181203Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.Type: ApplicationFiled: February 28, 2022Publication date: June 9, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Jen Chen, Kai-Shiung Hsu, Ding-I Liu, Jyh-nan Lin
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Patent number: 11322397Abstract: In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.Type: GrantFiled: October 25, 2019Date of Patent: May 3, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsiao-Min Chen, Jyh-Nan Lin, Kai-Shiung Hsu, Ding-I Liu
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Patent number: 11315829Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.Type: GrantFiled: June 2, 2020Date of Patent: April 26, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-Nan Lin, Chia-Yu Wu, Kai-Shiung Hsu, Ding-I Liu
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Patent number: 11264273Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.Type: GrantFiled: July 28, 2020Date of Patent: March 1, 2022Inventors: Chun-Jen Chen, Kai-Shiung Hsu, Ding-I Liu, Jyh-nan Lin
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Publication number: 20210351041Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.Type: ApplicationFiled: July 19, 2021Publication date: November 11, 2021Inventors: Hui-An HAN, Ding-I LIU, Yuh-Ta FAN, Kai-Shiung HSU
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Publication number: 20210233805Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.Type: ApplicationFiled: July 28, 2020Publication date: July 29, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Jen CHEN, Kai-Shiung Hsu, Ding-I Liu, Jyh-nan Lin
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Patent number: 11069534Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.Type: GrantFiled: October 15, 2019Date of Patent: July 20, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hui-An Han, Ding-I Liu, Yuh-Ta Fan, Kai-Shiung Hsu
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Patent number: 10978337Abstract: Aluminum-containing layers and systems and methods for forming the same are provided. In an embodiment, a method includes depositing an aluminum-containing layer on a substrate in a chamber by atomic layer deposition. The depositing further includes contacting the substrate with an aluminum-containing precursor in a first pulse having a first peak pulse flow rate and a first pulse width; contacting the substrate with a nitrogen-containing precursor; contacting the substrate with the aluminum-containing precursor in a second pulse having a second peak pulse flow rate and a second pulse width; and contacting the substrate with the nitrogen-containing precursor. The first peak pulse flow rate is greater than the second peak pulse flow rate. The first pulse width is smaller than the second pulse width.Type: GrantFiled: August 26, 2019Date of Patent: April 13, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jyh-nan Lin, Mu-Min Hung, Kai-Shiung Hsu, Ding-I Liu
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Publication number: 20210066122Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the n etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.Type: ApplicationFiled: June 2, 2020Publication date: March 4, 2021Inventors: Jyh-Nan Lin, Chia-Yu Wu, Kai-Shiung Hsu, Ding-I Liu
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Patent number: 10724140Abstract: A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.Type: GrantFiled: July 31, 2018Date of Patent: July 28, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Chan Lo, Yi-Fang Lai, Po-Hsiung Leu, Ding-I Liu, Si-Wen Liao, Kai-Shiung Hsu, Jheng-Uei Hsieh, Shian-Huei Lin, Jui-Fu Hsu, Cheng-Tsung Wu
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Publication number: 20200135868Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.Type: ApplicationFiled: October 15, 2019Publication date: April 30, 2020Inventors: Hui-An HAN, Ding-I LIU, Yuh-Ta FAN, Kai-Shiung HSU
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Publication number: 20200135553Abstract: In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.Type: ApplicationFiled: October 25, 2019Publication date: April 30, 2020Inventors: Hsiao-Min CHEN, Jyh-Nan LIN, Kai-Shiung HSU, Ding-I LIU
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Patent number: 10626499Abstract: A deposition device structure is provided. The deposition device structure includes a heater in a chamber. The deposition device structure also includes a shower head over the heater. The shower head includes holes extending from a top surface of the shower head to a bottom surface of the shower head. The bottom surface of the shower head faces the heater. The bottom surface of the shower head has a first section and a second section. The second section of the bottom surface is rougher than the first section of the bottom surface.Type: GrantFiled: October 5, 2017Date of Patent: April 21, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Chan Lo, Huan-Chieh Chen, Yi-Fang Lai, Keith Kuang-Kuo Koai, Chin-Feng Sun, Po-Hsiung Leu, Ding-I Liu, Kai-Shiung Hsu
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Publication number: 20200090986Abstract: Aluminum-containing layers and systems and methods for forming the same are provided. In an embodiment, a method includes depositing an aluminum-containing layer on a substrate in a chamber by atomic layer deposition. The depositing further includes contacting the substrate with an aluminum-containing precursor in a first pulse having a first peak pulse flow rate and a first pulse width; contacting the substrate with a nitrogen-containing precursor; contacting the substrate with the aluminum-containing precursor in a second pulse having a second peak pulse flow rate and a second pulse width; and contacting the substrate with the nitrogen-containing precursor. The first peak pulse flow rate is greater than the second peak pulse flow rate. The first pulse width is smaller than the second pulse width.Type: ApplicationFiled: August 26, 2019Publication date: March 19, 2020Inventors: Jhy-nan Lin, Mu-Min Hung, Kai-Shiung Hsu, Ding-I Liu