Patents by Inventor Kai-Shiung Hsu

Kai-Shiung Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210351041
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 11, 2021
    Inventors: Hui-An HAN, Ding-I LIU, Yuh-Ta FAN, Kai-Shiung HSU
  • Publication number: 20210233805
    Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.
    Type: Application
    Filed: July 28, 2020
    Publication date: July 29, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Jen CHEN, Kai-Shiung Hsu, Ding-I Liu, Jyh-nan Lin
  • Patent number: 11069534
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hui-An Han, Ding-I Liu, Yuh-Ta Fan, Kai-Shiung Hsu
  • Patent number: 10978337
    Abstract: Aluminum-containing layers and systems and methods for forming the same are provided. In an embodiment, a method includes depositing an aluminum-containing layer on a substrate in a chamber by atomic layer deposition. The depositing further includes contacting the substrate with an aluminum-containing precursor in a first pulse having a first peak pulse flow rate and a first pulse width; contacting the substrate with a nitrogen-containing precursor; contacting the substrate with the aluminum-containing precursor in a second pulse having a second peak pulse flow rate and a second pulse width; and contacting the substrate with the nitrogen-containing precursor. The first peak pulse flow rate is greater than the second peak pulse flow rate. The first pulse width is smaller than the second pulse width.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jyh-nan Lin, Mu-Min Hung, Kai-Shiung Hsu, Ding-I Liu
  • Publication number: 20210066122
    Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the n etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.
    Type: Application
    Filed: June 2, 2020
    Publication date: March 4, 2021
    Inventors: Jyh-Nan Lin, Chia-Yu Wu, Kai-Shiung Hsu, Ding-I Liu
  • Patent number: 10724140
    Abstract: A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Chan Lo, Yi-Fang Lai, Po-Hsiung Leu, Ding-I Liu, Si-Wen Liao, Kai-Shiung Hsu, Jheng-Uei Hsieh, Shian-Huei Lin, Jui-Fu Hsu, Cheng-Tsung Wu
  • Publication number: 20200135553
    Abstract: In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.
    Type: Application
    Filed: October 25, 2019
    Publication date: April 30, 2020
    Inventors: Hsiao-Min CHEN, Jyh-Nan LIN, Kai-Shiung HSU, Ding-I LIU
  • Publication number: 20200135868
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.
    Type: Application
    Filed: October 15, 2019
    Publication date: April 30, 2020
    Inventors: Hui-An HAN, Ding-I LIU, Yuh-Ta FAN, Kai-Shiung HSU
  • Patent number: 10626499
    Abstract: A deposition device structure is provided. The deposition device structure includes a heater in a chamber. The deposition device structure also includes a shower head over the heater. The shower head includes holes extending from a top surface of the shower head to a bottom surface of the shower head. The bottom surface of the shower head faces the heater. The bottom surface of the shower head has a first section and a second section. The second section of the bottom surface is rougher than the first section of the bottom surface.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Chan Lo, Huan-Chieh Chen, Yi-Fang Lai, Keith Kuang-Kuo Koai, Chin-Feng Sun, Po-Hsiung Leu, Ding-I Liu, Kai-Shiung Hsu
  • Publication number: 20200090986
    Abstract: Aluminum-containing layers and systems and methods for forming the same are provided. In an embodiment, a method includes depositing an aluminum-containing layer on a substrate in a chamber by atomic layer deposition. The depositing further includes contacting the substrate with an aluminum-containing precursor in a first pulse having a first peak pulse flow rate and a first pulse width; contacting the substrate with a nitrogen-containing precursor; contacting the substrate with the aluminum-containing precursor in a second pulse having a second peak pulse flow rate and a second pulse width; and contacting the substrate with the nitrogen-containing precursor. The first peak pulse flow rate is greater than the second peak pulse flow rate. The first pulse width is smaller than the second pulse width.
    Type: Application
    Filed: August 26, 2019
    Publication date: March 19, 2020
    Inventors: Jhy-nan Lin, Mu-Min Hung, Kai-Shiung Hsu, Ding-I Liu
  • Publication number: 20190032215
    Abstract: A deposition device structure is provided. The deposition device structure includes a heater in a chamber. The deposition device structure also includes a shower head over the heater. The shower head includes holes extending from a top surface of the shower head to a bottom surface of the shower head. The bottom surface of the shower head faces the heater. The bottom surface of the shower head has a first section and a second section. The second section of the bottom surface is rougher than the first section of the bottom surface.
    Type: Application
    Filed: October 5, 2017
    Publication date: January 31, 2019
    Inventors: Yen-Chan LO, Huan-Chieh CHEN, Yi-Fang LAI, Keith Kuang-Kuo KOAI, Chin-Feng SUN, Po-Hsiung LEU, Ding-I LIU, Kai-Shiung HSU
  • Patent number: 10161041
    Abstract: A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Chan Lo, Yi-Fang Lai, Po-Hsiung Leu, Ding-I Liu, Si-Wen Liao, Kai-Shiung Hsu, Jheng-Uei Hsieh, Shian-Huei Lin, Jui-Fu Hsu, Cheng-Tsung Wu
  • Publication number: 20180334747
    Abstract: A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Yen-Chan Lo, Yi-Fang Lai, Po-Hsiung Leu, Ding-I Liu, Si-Wen Liao, Kai-Shiung Hsu, Jheng-Uei Hsieh, Shian-Huei Lin, Jui-Fu Hsu, Cheng-Tsung Wu
  • Patent number: 9716044
    Abstract: The present disclosure provides a method of making an integrated circuit. The method includes forming a gate stack on a semiconductor substrate; forming a stressed contact etch stop layer (CESL) on the gate stack and on the semiconductor substrate; forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP) at a deposition temperature greater than about 440 C to drive out hydroxide (OH) group; forming a second dielectric material layer on the first dielectric material layer; etching to form contact holes in the first and second dielectric material layers; filling the contact holes with a conductive material; and performing a chemical mechanical polishing (CMP) process.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: July 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jen-Chi Chang, Chun-Li Lin, Kai-Shiung Hsu, Ming-Shiou Kuo, Wen-Long Lee, Po-Hsiung Leu, Ding-I Liu
  • Publication number: 20170107619
    Abstract: A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.
    Type: Application
    Filed: July 27, 2016
    Publication date: April 20, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Chan LO, Yi-Fang LAI, Po-Hsiung LEU, Ding-I LIU, Si-Wen LIAO, Kai-Shiung HSU, Jheng-Uei HSIEH, Shian-Huei LIN, Jui-Fu HSU, Cheng-Tsung WU
  • Publication number: 20130102117
    Abstract: One embodiment relates to a method of semiconductor manufacture. In this method, a strain inducing layer is formed over a p-type field effect transistor structure and an n-type field effect transistor structure. The strain inducing layer is removed from over the p-type field effect transistor while the strain inducing layer over the n-type field effect transistor is left in place. A treatment of the strain inducing layer over the n-type field effect transistor is performed after the strain-inducing layer has been removed from over the p-type field effect transistor.
    Type: Application
    Filed: October 21, 2011
    Publication date: April 25, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventor: Kai-Shiung Hsu
  • Publication number: 20130043539
    Abstract: The present disclosure provides a method of making an integrated circuit. The method includes forming a gate stack on a semiconductor substrate; forming a stressed contact etch stop layer (CESL) on the gate stack and on the semiconductor substrate; forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP) at a deposition temperature greater than about 440 C to drive out hydroxide (OH) group; forming a second dielectric material layer on the first dielectric material layer; etching to form contact holes in the first and second dielectric material layers; filling the contact holes with a conductive material; and performing a chemical mechanical polishing (CMP) process.
    Type: Application
    Filed: August 18, 2011
    Publication date: February 21, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jen-Chi Chang, Chun-Li Lin, Kai-Shiung Hsu, Ming-Shiou Kuo, Wen-Long Lee, Po-Hsiung Leu, Ding-I Liu