Abstract: Contact structures and methods of forming the same are provided. A method according to the present disclosure includes receiving a workpiece including a conductive feature embedded in a first dielectric layer, treating the workpiece with a nitrogen-containing plasma, after the treating, depositing a first etch stop layer (ESL) over the workpiece, depositing a second ESL over the first ESL, depositing a second dielectric layer over the second ESL, forming an opening through the second dielectric layer, the second ESL and the first ESL to expose the conductive feature, and forming a contact via in the opening. The first ESL includes aluminum nitride or silicon carbonitride and the second ESL includes aluminum oxide or silicon oxycarbide.

Abstract: A semiconductor device with a barrier layer between a gate structure and gate spacer layers, and a method of fabricating the same are disclosed. The a method includes forming a fin structure on a substrate, forming a polysilicon structure on the fin structure, performing a nitridation operation to form a barrier layer on the polysilicon structure and the fin structure, forming gate spacer layers on the barrier layer, forming a source/drain region in the fin structure and adjacent to the barrier layer, annealing the gate spacer layers, and replacing the polysilicon structure with a gate structure.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a fin base on a substrate, epitaxially growing a S/D region on the fin base, forming a contact opening on the S/D region, forming a semiconductor nitride layer on a sidewall of the contact opening, performing a densification process on the semiconductor nitride layer to form a densified semiconductor nitride layer, forming a silicide layer on an exposed surface of the S/D region in the contact opening, forming a contact plug in the contact opening, and forming a via structure in the contact plug.

Abstract: In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.

Abstract: The present disclosure describes a semiconductor device manufacturing apparatus and a method for handling contamination in the semiconductor device manufacturing apparatus. The semiconductor device manufacturing apparatus can include a deposition apparatus and a processor. The deposition apparatus can include a chamber, a detection module configured to detect impurities in the chamber, and a gas scrubbing device configured to remove the impurities. The processor can be configured to receive, from the detection module, an impurity characteristic associated with the impurities; compare the impurity characteristic to a baseline characteristic; and instruct the gas scrubbing device to supply a decontamination gas in the chamber based on the comparison of the impurity characteristic to the baseline characteristic.

Abstract: In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.

Abstract: A method of manufacturing a semiconductor device includes forming a gate dielectric layer over a channel region, and forming a first conductive layer over the gate dielectric layer. The method further includes forming a protective layer at a surface region of the first conductive layer by implanting a dopant into the surface region of the first conductive layer. The dopant is selected from a group consisting of boron, silicon, carbon, and nitrogen. The method also includes forming a metallic layer by applying a metal containing gas on the protective layer, and removing the metallic layer by a wet etching operation using a solution.

Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.

Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.

Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.

Abstract: Contamination from outgassing during a deposition process is addressed by a series of equipment enhancements, including throttle valves, a dual air curtain, and a residual gas analysis (RGA) monitor. The dual air curtain can be configured to flow a first gas during wafer processing and a second gas during wafer unloading, to re-direct and capture outgassed species. The dual air curtain and the throttle valves can be programmed in an automated feedback control system that utilizes data from the RGA monitor.

Abstract: The present disclosure describes a semiconductor device manufacturing apparatus and a method for handling contamination in the semiconductor device manufacturing apparatus. The semiconductor device manufacturing apparatus can include a deposition apparatus and a processor. The deposition apparatus can include a chamber, a detection module configured to detect impurities in the chamber, and a gas scrubbing device configured to remove the impurities. The processor can be configured to receive, from the detection module, an impurity characteristic associated with the impurities; compare the impurity characteristic to a baseline characteristic; and instruct the gas scrubbing device to supply a decontamination gas in the chamber based on the comparison of the impurity characteristic to the baseline characteristic.

Abstract: In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.

Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.

Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.

Abstract: In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.

Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.

Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.