Patents by Inventor Kai-Ting Shr

Kai-Ting Shr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153154
    Abstract: A coordinate generation system, a coordinate generation method, a computer readable recording medium with stored program, and a non-transitory computer program product are provided. The coordinate generation system includes processing units and a neural network module. The processing units are configured to obtain four vertex coordinates of an image. The vertex coordinates include first components and second components. The processing unit is configured to perform the following steps: obtaining first vector based on the first components of the four vertex coordinates and repeatedly concatenating the first vector so as to obtain a first input; obtaining second vector based on the second components of the four vertex coordinates and repeatedly concatenating the second vector so as to obtain a second input; and obtaining first output coordinate components and second output coordinate components of output coordinates based on the first input, the second input, and parameters of the neural network module.
    Type: Application
    Filed: January 17, 2023
    Publication date: May 9, 2024
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yu-Hsuan Hung, Chun-Fu Liao, Kai-Ting Shr
  • Publication number: 20230385217
    Abstract: A method for data access control among multiple nodes and a data access system are provided. The data access system includes a data interconnect controller circuit that allocates resources of one or more slaves by one or more masters according to operating parameters of an interleaver, and includes an intelligent control module that collects use efficiency data of the one or more slaves and obtains a current setting of the data interconnect controller circuit via a monitor. The monitor calculates scores of use efficiency data. The scores and the setting are inputted to a neural network model. Parameters of the neural network model are adjusted according to the scores, and a new setting generated by the neural network model is applied to the interleaver of the data interconnect controller circuit, so that the data interconnect controller circuit performs access control among the multiple nodes with the new setting.
    Type: Application
    Filed: May 30, 2023
    Publication date: November 30, 2023
    Inventors: YU-HSUAN HUNG, WEI-HAO FANG, KAI-TING SHR
  • Patent number: 11625344
    Abstract: A data transmission system has a master circuit, a slave circuit, and a transmission control circuit. The slave circuit stores a plurality of data in a first format. The master circuit processes data in a second format to perform a corresponding function. The transmission control circuit is coupled to the master circuit and the slave circuit. The transmission control circuit accesses a first datum from the slave circuit according to a first access command of the master circuit, converts the first datum in the first format into a first application datum in the second format, and transmits the first application datum to the master circuit.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: April 11, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventors: Kai-Ting Shr, Kuan-Hsing Lu
  • Patent number: 11481347
    Abstract: The present invention provides a data transmission system and resource allocation method thereof. The data transmission system is configured to: retrieve master device resource information and slave device performance information; based on a neural network model, determine at least one arbiter setting parameter according to the master device resource information and the slave device performance information; and determine resource allocation setting of at least one master device according to the at least one arbiter setting parameter.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: October 25, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Kai-Ting Shr, Min-Yen Hsieh, Chia-Wei Yu
  • Publication number: 20220109738
    Abstract: A data transmission system has a master circuit, a slave circuit, and a transmission control circuit. The slave circuit stores a plurality of data in a first format. The master circuit processes data in a second format to perform a corresponding function. The transmission control circuit is coupled to the master circuit and the slave circuit. The transmission control circuit accesses a first datum from the slave circuit according to a first access command of the master circuit, converts the first datum in the first format into a first application datum in the second format, and transmits the first application datum to the master circuit.
    Type: Application
    Filed: June 4, 2021
    Publication date: April 7, 2022
    Inventors: Kai-Ting Shr, Kuan-Hsing Lu
  • Publication number: 20210240647
    Abstract: The present invention provides a data transmission system and resource allocation method thereof. The data transmission system is configured to: retrieve master device resource information and slave device performance information; based on a neural network model, determine at least one arbiter setting parameter according to the master device resource information and the slave device performance information; and determine resource allocation setting of at least one master device according to the at least one arbiter setting parameter.
    Type: Application
    Filed: September 30, 2020
    Publication date: August 5, 2021
    Inventors: KAI-TING SHR, MIN-YEN HSIEH, CHIA-WEI YU
  • Patent number: 10698851
    Abstract: A data bit width converter is adapted to: convert first data using a first bit width as a data segment unit and second data using a second bit width as a data segment unit, and provide a cache to temporarily store third data, wherein the first bit width is not equal to the second bit width. The data bit width converter includes a slave, a cache, and a data reconstitution circuit. The slave is configured to read and write the second data. The cache is configured to read and write the third data. The data reconstitution circuit is configured to: convert the first data and the second data, and sequentially search the cache and the slave for the second data according to a searching program, to output the first data, and write the third data to the cache according to a temporary storage program.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: June 30, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Kai-Ting Shr, Chia-Wei Yu
  • Publication number: 20200192847
    Abstract: A data bit width converter is adapted to: convert first data using a first bit width as a data segment unit and second data using a second bit width as a data segment unit, and provide a cache to temporarily store third data, wherein the first bit width is not equal to the second bit width. The data bit width converter includes a slave, a cache, and a data reconstitution circuit. The slave is configured to read and write the second data. The cache is configured to read and write the third data. The data reconstitution circuit is configured to: convert the first data and the second data, and sequentially search the cache and the slave for the second data according to a searching program, to output the first data, and write the third data to the cache according to a temporary storage program.
    Type: Application
    Filed: March 27, 2019
    Publication date: June 18, 2020
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Kai-Ting Shr, Chia-Wei Yu