Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.

Abstract: A method for forming stressors in a semiconductor substrate is provided. The method includes providing a semiconductor substrate including a first device region and a second device region, forming shallow trench isolation (STI) regions with a high-shrinkage dielectric material in the first and the second device regions wherein the STI regions define a first active region in the first device region and a second active region in the second device region, forming an insulation mask over the STI region and the first active region in the first device region wherein the insulation mask does not extend over the second device region, and performing a stress-tuning treatment to the semiconductor substrate. The first active region and second active region have tensile stress and compressive stress respectively. An NMOS and a PMOS device are formed on the first and second active regions, respectively.

Abstract: A method for forming stressors in a semiconductor substrate is provided. The method includes providing a semiconductor substrate including a first device region and a second device region, forming shallow trench isolation (STI) regions with a high-shrinkage dielectric material in the first and the second device regions wherein the STI regions define a first active region in the first device region and a second active region in the second device region, forming an insulation mask over the STI region and the first active region in the first device region wherein the insulation mask does not extend over the second device region, and performing a stress-tuning treatment to the semiconductor substrate. The first active region and second active region have tensile stress and compressive stress respectively. An NMOS and a PMOS device are formed on the first and second active regions, respectively.

Abstract: Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their gate electrode sidewall spacers are fabricated such that the orientation of the intrinsic stress in the sidewall spacers is opposite to the stress created in the channel. An embodiment includes selectively patterning a compressive stress layer to form NMOS electrode sidewall spacers, wherein the compressive NMOS electrode sidewall spacers create a tensile stress in a NMOS channel. Another embodiment comprises selectively patterning a tensile stress layer to form tensile PMOS electrode sidewall spacers, wherein the PMOS electrode sidewall spacers create a compressive stress in a PMOS channel. Still other embodiments of the invention provide a semiconductor device having strained sidewall spacers. In one embodiment, a spacer having an intrinsic stress comprising one of tensile and compressive corresponds to a channel stress that is the other of tensile and compressive.