Abstract: A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. The system and method include storing data in one or more memory dependent architectural register numbers (MdArns), allocating the one or more MdArns to a MEMFILE, writing the allocated one or more MdArns to a map file, wherein the map file contains a MdArn map to enable subsequent access to an entry in the MEMFILE, upon receipt of a load request, checking a base, an index, a displacement and a match/hit via the map file to identify an entry in the MEMFILE and an associated store, and on a hit, providing the entry responsive to the load request from the one or more MdArns.

Abstract: A processor employs a prediction table at a front end of its instruction pipeline, whereby the prediction table stores address register and offset information for store instructions; and stack offset information for stack access instructions. The stack offset information for a corresponding instruction indicates the location of the data accessed by the instruction at the processor stack relative to a base location. The processor uses pattern matching to identify predicted dependencies between load/store instructions and predicted dependencies between stack access instructions. A scheduler unit of the instruction pipeline uses the predicted dependencies to perform store-to-load forwarding or other operations that increase efficiency and reduce power consumption at the processing system.

Abstract: A processor employs a prediction table at a front end of its instruction pipeline, whereby the prediction table stores address register and offset information for store instructions; and stack offset information for stack access instructions. The stack offset information for a corresponding instruction indicates the entry of the stack accessed by the instruction stack relative to a base entry. The processor uses pattern matching to identify predicted dependencies between load/store instructions and predicted dependencies between stack access instructions. A scheduler unit of the instruction pipeline uses the predicted dependencies to perform store-to-load forwarding or other operations that increase efficiency and reduce power consumption at the processing system.

Abstract: A processor employs a prediction table at a front end of its instruction pipeline, whereby the prediction table stores address register and offset information for store instructions; and stack offset information for stack access instructions. The stack offset information for a corresponding instruction indicates the location of the data accessed by the instruction at the processor stack relative to a base location. The processor uses pattern matching to identify predicted dependencies between load/store instructions and predicted dependencies between stack access instructions. A scheduler unit of the instruction pipeline uses the predicted dependencies to perform store-to-load forwarding or other operations that increase efficiency and reduce power consumption at the processing system.

Abstract: A processor employs a prediction table at a front end of its instruction pipeline, whereby the prediction table stores address register and offset information for store instructions; and stack offset information for stack access instructions. The stack offset information for a corresponding instruction indicates the entry of the stack accessed by the instruction stack relative to a base entry. The processor uses pattern matching to identify predicted dependencies between load/store instructions and predicted dependencies between stack access instructions. A scheduler unit of the instruction pipeline uses the predicted dependencies to perform store-to-load forwarding or other operations that increase efficiency and reduce power consumption at the processing system.

Abstract: A method and microprocessor are described for efficiently executing load instructions out-of-order (speculatively). The microprocessor includes an enhanced load store unit (LSU) and an enhanced instruction decoder. The enhanced LSU receives a plurality of out-of-order value addresses, and sends a resync signal to the enhanced instruction decoder when an execution error associated with a particular load instruction occurs. The enhanced instruction decoder stores a specific address associated with the particular load instruction, and increments a counter value that indicates how many times the resync signal was sent by the resync predictor. When the counter value reaches a predetermined threshold, subsequent load instructions from the specific address are executed in order (non-speculatively).

Abstract: A method and microprocessor are described for efficiently executing load instructions out-of-order (speculatively). The microprocessor includes an enhanced load store unit (LSU) and an enhanced instruction decoder. The enhanced LSU receives a plurality of out-of-order value addresses, and sends a resync signal to the enhanced instruction decoder when an execution error associated with a particular load instruction occurs. The enhanced instruction decoder stores a specific address associated with the particular load instruction, and increments a counter value that indicates how many times the resync signal was sent by the resync predictor. When the counter value reaches a predetermined threshold, subsequent load instructions from the specific address are executed in order (non-speculatively).