Patents by Inventor Kai Tzeng
Kai Tzeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250324623Abstract: A method of forming a semiconductor device includes: forming a passivation layer over a conductive pad that is disposed over a substrate; and forming an inductive component over the passivation layer, including: forming a first insulation layer and a first magnetic layer successively over the passivation layer; forming a first polymer layer over the first magnetic layer; forming a first conductive feature over the first polymer layer; forming a second polymer layer over the first polymer layer and the first conductive feature; patterning the second polymer layer, where after the patterning, a first sidewall of the second polymer layer includes multiple segments, where an extension of a first segment of the multiple segments intersects the second polymer layer; and after patterning the second polymer layer, forming a second insulation layer and a second magnetic layer successively over the second polymer layer.Type: ApplicationFiled: June 25, 2025Publication date: October 16, 2025Inventors: Mei-Chi Lee, Chi-Cheng Chen, Wei-Li Huang, Kai Tzeng, Chun Yi Wu, Ming-Da Cheng
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Patent number: 12426284Abstract: A method of forming a semiconductor device includes: forming a passivation layer over a conductive pad that is disposed over a substrate; and forming an inductive component over the passivation layer, including: forming a first insulation layer and a first magnetic layer successively over the passivation layer; forming a first polymer layer over the first magnetic layer; forming a first conductive feature over the first polymer layer; forming a second polymer layer over the first polymer layer and the first conductive feature; patterning the second polymer layer, where after the patterning, a first sidewall of the second polymer layer includes multiple segments, where an extension of a first segment of the multiple segments intersects the second polymer layer; and after patterning the second polymer layer, forming a second insulation layer and a second magnetic layer successively over the second polymer layer.Type: GrantFiled: May 31, 2022Date of Patent: September 23, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mei-Chi Lee, Chi-Cheng Chen, Wei-Li Huang, Kai Tzeng, Chun Yi Wu, Ming-Da Cheng
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Publication number: 20240234481Abstract: A method of forming a semiconductor device, the method including forming a first insulation layer over a substrate, depositing a first stack of magnetic layers over the first insulation layer, etching the first stack of magnetic layers such that a sidewall of the first stack of magnetic layers forms a stairstep pattern, forming a first photosensitive layer over the first stack of magnetic layers, the first insulation layer, and the substrate, wherein a thickness of the first photosensitive layer above a center of a first step of the stairstep pattern is different from a thickness of the first photosensitive layer above a center of a second step of the stairstep pattern, forming a first conductive feature over the first photosensitive layer, depositing a second insulation layer over the first photosensitive layer and the first conductive feature, and depositing a second magnetic layer over the second insulation layer.Type: ApplicationFiled: January 6, 2023Publication date: July 11, 2024Inventors: Szu-Shu Yang, Chun Yi Wu, Kai Tzeng, Yuh-Sen Chang, Chi-Cheng Chen, Chi-Chun Peng
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Publication number: 20230290809Abstract: A method of forming a semiconductor device includes: forming a passivation layer over a conductive pad that is disposed over a substrate; and forming an inductive component over the passivation layer, including: forming a first insulation layer and a first magnetic layer successively over the passivation layer; forming a first polymer layer over the first magnetic layer; forming a first conductive feature over the first polymer layer; forming a second polymer layer over the first polymer layer and the first conductive feature; patterning the second polymer layer, where after the patterning, a first sidewall of the second polymer layer includes multiple segments, where an extension of a first segment of the multiple segments intersects the second polymer layer; and after patterning the second polymer layer, forming a second insulation layer and a second magnetic layer successively over the second polymer layer.Type: ApplicationFiled: May 31, 2022Publication date: September 14, 2023Inventors: Mei-Chi Lee, Chi-Cheng Chen, Wei-Li Huang, Kai Tzeng, Chun Yi Wu, Ming-Da Cheng
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Patent number: 11139239Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including an interconnect structure overlying a substrate. The interconnect structure has a plurality of metal layers overlying over the substrate. A first dielectric layer overlies an uppermost surface of the interconnect structure. The first dielectric layer has opposing sidewalls defining a trench. A first magnetic layer is disposed within the trench and conformally extends along the opposing sidewalls. Conductive wires are disposed within the trench and overlie the first magnetic layer. A second magnetic layer overlies the first magnetic layer and the conductive wires. The second magnetic layer laterally extends from over a first sidewall of the opposing sidewalls to a second sidewall of the opposing sidewalls.Type: GrantFiled: October 1, 2019Date of Patent: October 5, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Kai Tzeng, Wei-Li Huang
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Patent number: 11086221Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.Type: GrantFiled: August 3, 2020Date of Patent: August 10, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
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Publication number: 20210098371Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including an interconnect structure overlying a substrate. The interconnect structure has a plurality of metal layers overlying over the substrate. A first dielectric layer overlies an uppermost surface of the interconnect structure. The first dielectric layer has opposing sidewalls defining a trench. A first magnetic layer is disposed within the trench and conformally extends along the opposing sidewalls. Conductive wires are disposed within the trench and overlie the first magnetic layer. A second magnetic layer overlies the first magnetic layer and the conductive wires. The second magnetic layer laterally extends from over a first sidewall of the opposing sidewalls to a second sidewall of the opposing sidewalls.Type: ApplicationFiled: October 1, 2019Publication date: April 1, 2021Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Kai Tzeng, Wei-Li Huang
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Publication number: 20200365645Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.Type: ApplicationFiled: August 3, 2020Publication date: November 19, 2020Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
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Patent number: 10734436Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.Type: GrantFiled: September 26, 2018Date of Patent: August 4, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
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Patent number: 10546889Abstract: Implementations of the disclosure provide a method of fabricating an image sensor device. The method includes forming first trenches in a first photoresist layer using a first photomask having a first pattern to expose a first surface of a substrate, directing ions into the exposed first substrate through the first trenches to form first isolation regions in the substrate, removing the first photoresist layer, forming second trenches in a second photoresist layer using a second photomask having a second pattern to expose a second surface of the substrate, the second pattern being shifted diagonally from the first pattern by half mask pitch, directing ions into the exposed second surface through the second trenches to form second isolation regions in the substrate, the first and second isolation regions being alternatingly disposed in the substrate, and the first and second isolation regions defining pixel regions therebetween, and removing the second photoresist layer.Type: GrantFiled: November 5, 2018Date of Patent: January 28, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
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Publication number: 20190088694Abstract: Implementations of the disclosure provide a method of fabricating an image sensor device. The method includes forming first trenches in a first photoresist layer using a first photomask having a first pattern to expose a first surface of a substrate, directing ions into the exposed first substrate through the first trenches to form first isolation regions in the substrate, removing the first photoresist layer, forming second trenches in a second photoresist layer using a second photomask having a second pattern to expose a second surface of the substrate, the second pattern being shifted diagonally from the first pattern by half mask pitch, directing ions into the exposed second surface through the second trenches to form second isolation regions in the substrate, the first and second isolation regions being alternatingly disposed in the substrate, and the first and second isolation regions defining pixel regions therebetween, and removing the second photoresist layer.Type: ApplicationFiled: November 5, 2018Publication date: March 21, 2019Inventors: Wei-Chao CHIU, Chih-Chien WANG, Feng-Jia SHIU, Ching-Sen KUO, Chun-Wei CHANG, Kai TZENG
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Publication number: 20190027530Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.Type: ApplicationFiled: September 26, 2018Publication date: January 24, 2019Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
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Publication number: 20190027519Abstract: Various examples of a technique for forming a pattern for substrate fabrication are disclosed herein. In an example, a method includes receiving a substrate. A patterned resist is formed on the substrate and has a trench defined therein. A dielectric is deposited on the patterned resist and within the trench such that the dielectric narrows a width of the trench to further define the trench. A fabrication process is performed on a region of the substrate underlying the trench defined by the dielectric.Type: ApplicationFiled: July 18, 2017Publication date: January 24, 2019Inventors: Wei-Chao Chiu, Kai Tzeng, Chih-Chien Wang, Chun-Wei Chang, Ching-Sen Kuo, Feng-Jia Shiu, Cheng-Ta Wu
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Patent number: 10186542Abstract: Various examples of a technique for forming a pattern for substrate fabrication are disclosed herein. In an example, a method includes receiving a substrate. A patterned resist is formed on the substrate and has a trench defined therein. A dielectric is deposited on the patterned resist and within the trench such that the dielectric narrows a width of the trench to further define the trench. A fabrication process is performed on a region of the substrate underlying the trench defined by the dielectric.Type: GrantFiled: July 18, 2017Date of Patent: January 22, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Chao Chiu, Kai Tzeng, Chih-Chien Wang, Chun-Wei Chang, Ching-Sen Kuo, Feng-Jia Shiu, Cheng-Ta Wu
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Patent number: 10121811Abstract: Implementations of the disclosure provide a method of fabricating an image sensor device. The method includes forming first trenches in a first photoresist layer using a first photomask having a first pattern to expose a first surface of a substrate, directing ions into the exposed first substrate through the first trenches to form first isolation regions in the substrate, removing the first photoresist layer, forming second trenches in a second photoresist layer using a second photomask having a second pattern to expose a second surface of the substrate, the second pattern being shifted diagonally from the first pattern by half mask pitch, directing ions into the exposed second surface through the second trenches to form second isolation regions in the substrate, the first and second isolation regions being alternatingly disposed in the substrate, and the first and second isolation regions defining pixel regions therebetween, and removing the second photoresist layer.Type: GrantFiled: August 25, 2017Date of Patent: November 6, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
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Patent number: 10090357Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.Type: GrantFiled: March 7, 2016Date of Patent: October 2, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
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Publication number: 20170186808Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.Type: ApplicationFiled: March 7, 2016Publication date: June 29, 2017Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
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Patent number: 9401384Abstract: A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements, wherein a top portion of the deep doped region is below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with the top portion of the deep doped region.Type: GrantFiled: October 8, 2015Date of Patent: July 26, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chi Fu, Kai Tzeng, Wen-Chen Lu
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Publication number: 20160027839Abstract: A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements, wherein a top portion of the deep doped region is below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with the top portion of the deep doped region.Type: ApplicationFiled: October 8, 2015Publication date: January 28, 2016Inventors: Shih-Chi FU, Kai TZENG, Wen-Chen LU
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Patent number: 9171876Abstract: A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate. The method includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements and starting at a distance below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with a top portion of the deep doped region.Type: GrantFiled: May 30, 2014Date of Patent: October 27, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chi Fu, Kai Tzeng, Wen-Chen Lu