Abstract: The invention relates to a high-strength copper-nickel-tin alloy with excellent castability, hot workability and cold workability, high resistance to abrasive wear, adhesive wear and fretting wear and improved resistance to corrosion and stress relaxation stability, consisting of (in weight %): 2.0-10.0% Ni, 2.0-10.0% Sn, 0.01-1.0% Fe, 0.01-0.8% Mg, 0.01-2.5% Zn, 0.01-1.5% Si, 0.002-0.45% B, 0.004-0.3% P, selectively up to a maximum of 2.0% Co, selectively up to a maximum of 0.25% Pb, the residue being copper and unavoidable impurities, characterised in that—the ratio Si/B of the element contents in wt. % of the elements silicon and boron is a minimum 0.4 and a maximum 8; such that the copper-nickel-tin alloy has Si-containing and B-containing phases and phases of the systems Ni—Si—B, Ni—B, Fe—B, Ni—P, Fe—P, Mg—P, Ni—Si, Mg—Si and other Fe-containing phases and Mg-containing phases which significantly improve the processing properties and use properties of the alloy.

Abstract: A data processor comprising a plurality of registers, and instruction execution circuitry having an associated instruction set, wherein the instruction set includes an instruction specifying at least a mask operand, a register operand and an immediate value operand, and the instruction execution circuitry, in response to an instance of the instruction, determines a Boolean value based on the mask operand and sets a respective one of a plurality of registers specified by the register operand of the instance to a value of the immediate value operand if the Boolean value is true. The instruction execution circuitry, in response to the instance of the instruction, may set the respective one of the plurality of registers specified by the register operand of the instance to zero if the Boolean value is false.

Abstract: The invention relates to a high-strength as-cast copper alloy containing tin, with excellent hot-workability and cold-workability properties, high resistance to abrasive wear, adhesive wear and fretting wear, and improved corrosion resistance and stress relaxation resistance, consisting (in wt. %) of: 4.0 to 23.0% Sn, 0.05 to 2.0% Si, 0.01 to 1.0% Al, 0.005 to 0.6% B, 0.001 to 0.08% P, optionally up to a maximum of 2.0% Zn, optionally up to a maximum of 0.6% Fe, optionally up to a maximum of 0.5% Mg, optionally up to a maximum of 0.25% Pb, with the remainder being copper and inevitable impurities, characterised in that the ratio of Si/B of the element content of the elements silicon and boron lies between 0.3 and 10. The invention also relates to a casting variant and a further-processed variant of the tin-containing copper alloy, a production method, and the use of the alloy.

Abstract: The invention relates to a high-strength as-cast copper alloy containing tin, with excellent hot-workability and cold-workability properties, high resistance to abrasive wear, adhesive wear and fretting wear, and improved corrosion resistance and stress relaxation resistance, consisting (in wt. %) of: 4.0 to 23.0% Sn, 0.05 to 2.0% Si, 0.005 to 0.6 B, 0.001 to 0.08% P, optionally up to a maximum of 2.0% Zn, optionally up to a maximum of 0.6% Fe, optionally up to a maximum of 0.5% Mg, optionally up to a maximum of 0.25% Pb, with the remainder being copper and inevitable impurities, characterised in that the ratio of Si/B of the element content of the elements silicon and boron lies between 0.3 and 10. The invention also relates to a casting variant and a further-processed variant of the tin-containing copper alloy, a production method, and the use of the alloy.

Abstract: Electrical connection element containing a copper-zinc alloy. The copper-zinc alloy comprises (in percent by weight): 28.0 to 36.0% Zn, 0.5 to 1.5% Si, 1.5 to 2.5% Mn, 0.2 to 1.0% Ni, 0.5 to 1.5% Al, 0.1 to 1.0% Fe, optionally also up to a maximum of 0.1% Pb, optionally also up to a maximum of 0.1% P, optionally up to a maximum of 0.08% S, the remainder being Cu and inevitable impurities. According to the invention, mixed silicides containing iron, nickel and manganese are incorporated in the matrix. The structure comprises an ?-matrix, which contains inclusions of ?-phase from 5 up to 45 percent by volume and of mixed silicides containing iron, nickel and manganese up to 20 percent by volume. The structure further comprises mixed silicides containing iron, nickel and manganese having a stemmed shape and iron and nickel enriched mixed silicides having a globular shape.

Abstract: A data processing system including multiple processors with a hierarchical cache structure comprising multiple levels of cache between the processors and a main memory, wherein at least one page mover is positioned closer to the main memory and is connected to the cache memories of the at least one shared cache level (L2, L3, L4), the main memory and to the multiple processors to move data between the cache memories of the at least one shared cache level, the main memory and the processors. In response to a request from one of the processors, the at least one page mover fetches data of a storage area line-wise from at least one of the following memories: the cache memories and the main memory maintaining multiple processor cache memory access coherency.

Abstract: A data processor comprising a plurality of registers, and instruction execution circuitry having an associated instruction set, wherein the instruction set includes an instruction specifying at least a mask operand, a register operand and an immediate value operand, and the instruction execution circuitry, in response to an instance of the instruction, determines a Boolean value based on the mask operand and sets a respective one of a plurality of registers specified by the register operand of the instance to a value of the immediate value operand if the Boolean value is true. The instruction execution circuitry, in response to the instance of the instruction, may set the respective one of the plurality of registers specified by the register operand of the instance to zero if the Boolean value is false.

Abstract: A data processor comprising a plurality of registers, and instruction execution circuitry having an associated instruction set, wherein the instruction set includes an instruction specifying at least a mask operand, a register operand and an immediate value operand, and the instruction execution circuitry, in response to an instance of the instruction, determines a Boolean value based on the mask operand and sets a respective one of a plurality of registers specified by the register operand of the instance to a value of the immediate value operand if the Boolean value is true. The instruction execution circuitry, in response to the instance of the instruction, may set the respective one of the plurality of registers specified by the register operand of the instance to zero if the Boolean value is false.

Abstract: A verification method is provided and includes randomly choosing a hardware executed instruction in a predefined program to force Opcode Compare on, determining an identity of a corresponding opcode from the chosen instruction and initializing Opcode Compare logic to trap the chosen instruction to firmware and creating firmware to initiate performance of hardware verification in the firmware and re-initiating performance of the hardware verification in hardware.

Abstract: A data processing system including multiple processors with a hierarchical cache structure comprising multiple levels of cache between the processors and a main memory, wherein at least one page mover is positioned closer to the main memory and is connected to the cache memories of the at least one shared cache level (L2, L3, L4), the main memory and to the multiple processors to move data between the cache memories of the at least one shared cache level, the main memory and the processors. In response to a request from one of the processors, the at least one page mover fetches data of a storage area line-wise from at least one of the following memories: the cache memories and the main memory maintaining multiple processor cache memory access coherency.

Abstract: An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model includes at least one execution unit for executing at least one instruction of a test file. The method includes tracking each execution of each of the at least one instruction, monitoring relevant signals in each simulation cycle, maintaining information about the execution of the at least one instruction, wherein the maintained information includes a determination of an execution length of a completely executed instruction, matching the maintained information about the completely executed instruction against a set of trap elements provided by the user through a trap file, and collecting the maintained information about the completely executed instruction in a monitor file in response to a match found between the maintained information and at least one of the trap elements.

Abstract: A mechanism is provided for verifying design modifications to a simulation design unit included within a simulation model of an integrated electronic device. A modified description is received of a simulation design unit that failed to meet an expected physical property value during an initial simulation of the entire integrated electronic device. A simulation of the simulation design unit is executed using a list of identified input signals from a trace file. The trace file is generated during the initial simulation and indicates state values for the list of identified input signals. A determination is made as to whether the simulation of the simulation design unit fails to meet the expected physical property value. An indication is generated that modifications made to an initial description of the simulation design unit are successful in response to the simulation of the simulation design unit meeting the expected physical property value.

Abstract: A mechanism is provided for verifying a register-transfer level design of an execution unit. A set of instruction records associated with a test case are generated and stored in a buffer. For each instruction record in the set of instruction records associated with the test case: the instruction record is retrieved from the buffer and sent to both a reference model and an execution unit in the data processing system. Separately, the reference model and the execution unit execute the instruction record and send results of the execution of the instruction record to a result checker in the data processing system. The result checker compares the two results and, responsive to a mismatch in the results, a failure of the test case is indicted, the verification of the test case is stopped, and all data associated with the test case is output from the buffer for analysis.

Abstract: An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model includes at least one execution unit for executing at least one instruction of a test file. The method includes tracking each execution of each of the at least one instruction, monitoring relevant signals in each simulation cycle, maintaining information about the execution of the at least one instruction, wherein the maintained information includes a determination of an execution length of a completely executed instruction, matching the maintained information about the completely executed instruction against a set of trap elements provided by the user through a trap file, and collecting the maintained information about the completely executed instruction in a monitor file in response to a match found between the maintained information and at least one of the trap elements.

Abstract: The invention relates to a copper-tin multicomponent bronze consisting of (in % by weight): 0.5 to 14.0% Sn, 0.01 to 8.0% Zn, 0.01 to 0.8% Cr, 0.05 to 2.0% Al, 0.01 to 2.0% Si, optionally in addition up to a maximum of 0.1 to 3.0% Mn and optionally in addition up to a maximum of 0.08% P and optionally in addition up to a maximum of 0.08% S, remainder copper and unavoidable impurities, wherein, in the structure, silicides and/or chromium particles are deposited, which are surrounded by a tin film in the form of a highly tin-containing accumulation. A further aspect of the invention relates to a process for producing strips, plates, bolts, wires, rods, tubes and profiles of the copper-tin multicomponent bronze according to the invention, and also to a use.

Abstract: An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model includes at least one execution unit for executing at least one instruction of a test file. The method includes tracking each execution of each of the at least one instruction, monitoring relevant signals in each simulation cycle, maintaining information about the execution of the at least one instruction, wherein the maintained information includes a determination of an execution length of a completely executed instruction, matching the maintained information about the completely executed instruction against a set of trap elements provided by the user through a trap file, and collecting the maintained information about the completely executed instruction in a monitor file in response to a match found between the maintained information and at least one of the trap elements.

Abstract: A verification method is provided and includes randomly choosing a hardware executed instruction in a predefined program to force Opcode Compare on, determining an identity of a corresponding opcode from the chosen instruction and initializing Opcode Compare logic to trap the chosen instruction to firmware and creating firmware to initiate performance of hardware verification in the firmware and re-initiating performance of the hardware verification in hardware.

Abstract: A mechanism is provided for verifying a register-transfer level design of an execution unit a set of instruction records associated with a test case are generated and stored in a buffer. For each instruction record in the set of instruction records associated with the test case: the instruction record is retrieved from the buffer and sent to both a reference model and an execution unit in the data processing system. Separately, the reference model and the execution unit execute the instruction record and send results of the execution of the instruction record to a result checker in the data processing system.

Abstract: A new and convenient methodology for proving the correctness of multiplier and multiply-accumulate circuit designs in a full custom design flow. Such an approach utilizes a basic description of the implemented algorithm, which is created in early phases of the design flow and requires only little extra work for the designer who spends most of the time in full-custom optimizations. Such an approach also defines arithmetic circuit at the arithmetic bit level and allows for the generation of a gate level netlist. Given a structural similarity between the specification and design under verification, a large amount of structural similarity between the generated netlists is obtained so that a standard equivalence checker can be utilized to verify the design against the specification.

Abstract: A method of generating a test case from a given test case structure, the method including generating instructions for the given test case structure, propagating predefined results in a backwards manner, randomly generating remaining operands of the test case structure in a forwards manner, and calculating a result for the test case by determining missing input operands and storing these input operands in both the temporary register file and the initial register file, and calculating missing results and storing all results in the temporary register file.