Patents by Inventor Kai-Wei Yen

Kai-Wei Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240113032
    Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.
    Type: Application
    Filed: April 25, 2023
    Publication date: April 4, 2024
    Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
  • Patent number: 11942445
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a surface. The semiconductor device includes a conductive pad over a portion of the surface. The conductive pad has a curved top surface, and a width of the conductive pad increases toward the substrate. The semiconductor device includes a device over the conductive pad. The semiconductor device includes a solder layer between the device and the conductive pad. The solder layer covers the curved top surface of the conductive pad, and the conductive pad extends into the solder layer.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-En Yen, Chin-Wei Kang, Kai-Jun Zhan, Wen-Hsiung Lu, Cheng-Jen Lin, Ming-Da Cheng, Mirng-Ji Lii
  • Patent number: 9231810
    Abstract: A carrier frequency offset (CFO) calibration method for calibrating a CFO of a receiver is proposed. The CFO calibration method includes: receiving at least one CFO estimation value generated by digital CFO estimation; generating a CFO adjustment value according to the at least one CFO estimation value; and adjusting an oscillation frequency of an oscillator of the receiver according to the CFO adjustment value.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: January 5, 2016
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chih-Yung Wu, Kai-Wei Yen, Chung-Yao Chang
  • Publication number: 20150156048
    Abstract: A carrier frequency offset (CFO) calibration method for calibrating a CFO of a receiver is proposed. The CFO calibration method includes: receiving at least one CFO estimation value generated by digital CFO estimation; generating a CFO adjustment value according to the at least one CFO estimation value; and adjusting an oscillation frequency of an oscillator of the receiver according to the CFO adjustment value.
    Type: Application
    Filed: November 24, 2014
    Publication date: June 4, 2015
    Inventors: Chih-Yung Wu, Kai-Wei Yen, Chung-Yao Chang