Patents by Inventor Kai Xiao

Kai Xiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210035349
    Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.
    Type: Application
    Filed: August 18, 2020
    Publication date: February 4, 2021
    Inventors: Karthik VAIDYANATHAN, Michael APODACA, Thomas RAOUX, Carsten BENTHIN, Kai XIAO, Carson BROWNLEE, Joshua BARCZAK
  • Publication number: 20210035270
    Abstract: Systems, apparatuses and methods may provide for technology that identifies, at an image post-processor, unresolved surface data and identifies, at the image post-processor, control data associated with the unresolved surface data. Additionally, the technology may resolve, at the image post-processor, the unresolved surface data and the control data into a final image.
    Type: Application
    Filed: July 15, 2020
    Publication date: February 4, 2021
    Inventors: Tomer Bar-On, Hugues Labbe, Adam T. Lake, Kai Xiao, Ankur N. Shah, Johannes Guenther, Abhishek R. Appu, Joydeep Ray, Deepak S. Vembar, ElMoustapha Ould-Ahmed-Vall
  • Patent number: 10908865
    Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Deepak S. Vembar, Atsuo Kuwahara, Chandrasekaran Sakthivel, Radhakrishnan Venkataraman, Brent E. Insko, Anupreet S. Kalra, Hughes Labbe, Altug Koker, Michael Apodaca, Kai Xiao, Jeffery S. Boles, Adam T. Lake, David M. Cimini, Balaji Vembu, Elmoustapha Ould-Ahmed-Vall, Jacek Kwiatkowski, Philip R. Laws, Ankur N. Shah, Abhishek R. Appu, Joydeep Ray, Wenyin Fu, Nikos Kaburlasos, Prasoonkumar Surti, Bhushan M. Borole
  • Publication number: 20210012553
    Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Inventors: Michael APODACA, Carsten BENTHIN, Kai XIAO, Carson BROWNLEE, Timothy ROWLEY, Joshua BARCZAK, Travis SCHLUESSLER
  • Patent number: 10893299
    Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to encode surface normals data with point cloud geometry data included in the video bit stream data for reconstruction of objects within the video bit stream data based on the surface normals data and a memory communicatively coupled to the one or more processors.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Jill Boyce, Scott Janus, Itay Kaufman, Archie Sharma, Stanley Baran, Michael Apodaca, Prasoonkumar Surti, Srikanth Potluri, Barnan Das, Hugues Labbe, Jong Dae Oh, Gokcen Cilingir, Maria Bortman, Tzach Ashkenazi, Jonathan Distler, Atul Divekar, Mayuresh M. Varerkar, Narayan Biswal, Nilesh V. Shah, Atsuo Kuwahara, Kai Xiao, Jason Tanner, Jeffrey Tripp
  • Publication number: 20200402291
    Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.
    Type: Application
    Filed: June 29, 2020
    Publication date: December 24, 2020
    Applicant: Intel Corporation
    Inventors: KAI XIAO, MICHAEL APODACA, CARSON BROWNLEE, THOMAS RAOUX, JOSHUA BARCZAK, GABOR LIKTOR
  • Publication number: 20200372720
    Abstract: An electronic apparatus, a wireless communication system, a wireless communication method, and a computer-readable storage medium are provided. The electronic apparatus includes a processing circuit configured to: determine a current audiovisual angle of a user; compare the current audiovisual angle of the user with an expected audiovisual angle, and generate indication information for directing the user to the expected audiovisual angle, and provide the indication information to the user. The indication information directs the user to the expected audiovisual angle by using a direct direction indication and an indirect direction indication. With the electronic apparatus, the wireless communication system, the wireless communication method, and the computer-readable storage medium, the user can obtain a better visual feeling, and thus the user experience can be improved.
    Type: Application
    Filed: August 13, 2020
    Publication date: November 26, 2020
    Applicant: Sony Corporation
    Inventors: Kai XIAO, Qi ZHENG, Zhongsheng HONG, Jia HAN
  • Patent number: 10846814
    Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to decode occupancy map data and auxiliary patch information and generate a plurality of patch video frames based on patch data decoded from the occupancy map data and auxiliary patch information, and a memory communicatively coupled to the one or more processors.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Jill Boyce, Sang-hee Lee, Scott Janus, Stanley Baran, Michael Apodaca, Prasoonkumar Surti, Srikanth Potluri, Atsuo Kuwahara, Kai Xiao, Jason Tanner, Gokcen Cilingir, Archie Sharma, Jeffrey Tripp, Jason Ross, Barnan Das
  • Patent number: 10846918
    Abstract: Systems, apparatuses, and methods may provide for technology to render and compress stereoscopic graphical data. In one example, the technology identifies, from graphical data associated with a stereoscopic image defined by a first perspective view and a second perspective view, a background region and a foreground region of a graphical scene in the stereoscopic image, renders graphical data of the identified background region for the first perspective view, and compresses the rendered graphical data.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: John G. Gierach, Hugues Labbe, Tomer Bar-On, Adam T. Lake, Kai Xiao, Ankur N. Shah, Philip R. Laws, Devan Burke, Abhishek R. Appu, Peter L. Doyle, Elmoustapha Ould-Ahmed-Vall, Travis T. Schluessler, Altug Koker
  • Patent number: 10839589
    Abstract: A mechanism is described for facilitating enhanced immersive media pipeline for correction of artifacts and clarity of objects in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to extract semantic data relating to objects in a scene captured through one or more cameras, where the objects include distortions, and form, based on the semantic data, a three-dimensional (3D) model of contents of the scene, where the contents include the objects. The one or more processors are further to encode the 3D model including the contents and the semantic data into an encoded file having encoded contents and encoded semantic data and transmit the encoded file over an immersive media pipeline to facilitate correction of the distortions and rendering the scene including the objects without the distortions.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: November 17, 2020
    Assignee: INTEL CORPORATION
    Inventors: Gokcen Cilingir, Atsuo Kuwahara, Narayan Biswal, James Holland, Sang-Hee Lee, Jason Tanner, Mayuresh Varerkar, Kai Xiao
  • Publication number: 20200357092
    Abstract: An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 12, 2020
    Applicant: Intel Corporation
    Inventors: Hugues Labbe, Tomer Bar-On, Kai Xiao, Ankur N. Shah, John G. Gierach
  • Publication number: 20200334779
    Abstract: Implementations of the present specification provide a fraud gang identification method and device. The method includes: constructing a relational network that includes a plurality of nodes; performing cluster discovery based on the relational network to obtain at least one fraud gang included in the relational network, each fraud gang including the plurality of nodes; determining a weak node from the nodes included in the fraud gang, the weak node being a node whose association with the fraud gang meets a weak association criterion; and removing the weak node from the fraud gang to identify a final target fraud gang.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 22, 2020
    Inventors: Changhua MENG, Kai XIAO, Lujia CHEN, Weiqiang WANG
  • Publication number: 20200334896
    Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.
    Type: Application
    Filed: May 4, 2020
    Publication date: October 22, 2020
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer Kp, Jonathan Kennedy, Abhishek R. Appu, Jeffery S. Boles, Balaji Vembu, Michael Apodaca, Slawomir Grajewski, Gabor Liktor, David M. Cimini, Andrew T. Lauritzen, Travis T. Schluessler, Murali Ramadoss, Abhishek Venkatesh, Joydeep Ray, Kai Xiao, Ankur N. Shah, Altug Koker
  • Patent number: 10783603
    Abstract: An embodiment of a graphics apparatus may include a tile candidate identifier to determine if a compute kernel is a tile candidate, and a compute kernel tiler communicatively coupled to the tile candidate identifier to tile the compute kernel if the compute kernel is determined to be a tile candidate. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Abhishek Venkatesh, Prasoonkumar Surti, Slawomir Grajewski, Louis Feng, Kai Xiao, Tomasz Janczak, Devan Burke, Travis T. Schluessler
  • Publication number: 20200292603
    Abstract: Technologies for verifying a de-embedder for interconnect measurement include a verification compute device. The verification compute device is to measure a first signal transmitted through a single device under test and measure a second signal transmitted through a duplicated set of devices under test. Each device under test in the duplicated set is substantially identical to the single device under test. Additionally, the verification compute device is to apply a de-embedder to the measured first signal to remove an effect of test fixtures on the measured first signal, apply the de-embedder to the measured second signal to remove the effect of the test fixtures on the measured second signal, concatenate the de-embedded first signal with itself to generate a concatenated de-embedded first signal, and compare the concatenated de-embedded first signal with the de-embedded second signal to determine whether the concatenated de-embedded first signal matches the de-embedded second signal.
    Type: Application
    Filed: February 24, 2020
    Publication date: September 17, 2020
    Inventors: Xiaoning Ye, Kai Xiao
  • Patent number: 10777011
    Abstract: An electronic apparatus, a wireless communication system, a wireless communication method, and a computer-readable storage medium are provided. The electronic apparatus includes a processing circuit configured to: determine a current audiovisual angle of a user; compare the current audiovisual angle of the user with an expected audiovisual angle, and generate indication information for directing the user to the expected audiovisual angle, and provide the indication information to the user. The indication information directs the user to the expected audiovisual angle by using a direct direction indication and an indirect direction indication. With the electronic apparatus, the wireless communication system, the wireless communication method, and the computer-readable storage medium, the user can obtain a better visual feeling, and thus the user experience can be improved.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: September 15, 2020
    Assignee: SONY CORPORATION
    Inventors: Kai Xiao, Qi Zheng, Zhongsheng Hong, Jia Han
  • Patent number: 10762592
    Abstract: Embodiments described herein provide an apparatus comprising a processor to divide a first projection into a plurality of regions, the plurality of regions comprising a plurality of pixels, detect errant visual content in a first region in the plurality of regions, determine a detail frequency rating for the first region, and apply one of a first rendering technique to the first region in the plurality of regions when the detail frequency rating for the first region in the plurality of regions fails to meet a detail frequency threshold or a second rendering technique to the first region in the plurality of regions when the detail frequency rating for the first region in the plurality of regions meets a detail frequency threshold. Other embodiments may be described and claimed.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: September 1, 2020
    Assignee: INTEL CORPORATION
    Inventors: Kai Xiao, Gokcen Cilingir, Jason Tanner, Sang-Hee Lee, Atsuo Kuwahara
  • Patent number: 10762668
    Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Carson Brownlee, Carsten Benthin, Joshua Barczak, Kai Xiao, Michael Apodaca, Prasoonkumar Surti, Thomas Raoux
  • Patent number: 10755469
    Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Karthik Vaidyanathan, Michael Apodaca, Thomas Raoux, Carsten Benthin, Kai Xiao, Carson Brownlee, Joshua Barczak
  • Publication number: 20200257532
    Abstract: Systems, apparatuses and methods may provide for technology that activates a first context on a graphics processor and detects a context switch condition with respect to the first context. Additionally, a second context may be activated, in response to the context switch condition, on the graphics processor while the first context is active on the graphics processor. In one example, activating the second context includes adding a group identifier to a plurality of threads corresponding to the second context and launching the plurality of threads with the group identifier on the graphics processor.
    Type: Application
    Filed: February 19, 2020
    Publication date: August 13, 2020
    Inventors: Altug Koker, Michael Apodaca, Kai Xiao, Chandrasekaran Sakthivel, Jeffery S. Boles, Adam T. Lake, Abhishek R. Appu