Abstract: A low-cost and high-strength Bi-based superconducting wire/tape and a preparation method thereof, the preparation method includes: 1. subjecting a first Bi-based superconducting wire/tape to electrochemical silver reduction to remove a Ag alloy layer to obtain a second Bi-based superconducting wire/tape; and 2. subjecting the second Bi-based superconducting wire/tape to surface enhancement, such that a Cu layer is formed to obtain the low-cost and high-strength Bi-based superconducting wire/tape. An electrochemical silver reduction technology combines with an electrochemical additive method to remove a Ag alloy layer on a surface of a Bi-based superconducting wire/tape and coat a high-strength Cu layer, such that a low-cost and high-strength Bi-based superconducting wire/tape can be prepared, which reduces a preparation cost and improves a strength of a Bi-based superconducting wire/tape to meet the application requirements of large super-strong magnets.

Abstract: An ESD protection circuit is coupled to a first pad and includes an ESD detection circuit, a P-type transistor, an N-type transistor, and a discharge circuit. The ESD detection circuit determines whether an ESD event occurs on the first pad to generate a detection signal at a first node. The P-type transistor comprises a source coupled to the first pad, a drain coupled to a second node, and a gate coupled to the first node. The N-type transistor comprises a drain coupled to the second node, a source coupled to a ground, and a gate coupled to a second pad. The discharge circuit is coupled between the first pad and the ground and controlled by a driving signal at the second node. When the ESD protection circuit is in an operation mode, the first pad receives a first voltage, and a second pad receives a second voltage.

Abstract: A method and a device for nidus recognition in a neuroimage, an electronic apparatus, and a storage medium are provided. A collection of neuroimages to be recognized, including a first structural image, a first nidus image, and a first metabolic image, is determined, and then image preprocessing is performed on the collection of neuroimages to acquire a collection of object images including a second structural image, a second nidus image, and a second metabolic image. The collection of object images is input into a trained three-dimensional convolutional neural network to acquire a position of a nidus of the target object, and then the position of the nidus is labeled on the first structural image based on the position of the nidus of the target object to acquire and display an image of the position of the nidus.

Abstract: The display panel comprises: a plurality of pixels arranged in an array. Each pixel comprises a plurality of subpixels. The plurality of pixels arranged in an array comprise: a plurality of pixel rows. Each pixel row comprises a plurality of subpixels arranged in a first direction. The plurality of pixel rows extend in a second direction. The first direction intersects with the second direction. The display panel comprises: a first array substrate and a first opposing substrate arranged opposite to each other, and a first liquid crystal layer located between the first array substrate and the first opposing substrate. The first array substrate comprises: a plurality of first driving transistors arranged in an array. At least one pixel is arranged between two adjacent first driving transistors in the first direction. The first opposing substrate comprises: a plurality of light shielding portions in one-to-one correspondence to the first driving transistors.

Abstract: This application provides a switched capacitor circuit SC and an electronic device. In the SC, when the SC circuit works in different voltage step-down modes, voltage step-down is separately performed in a ratio of 4:1, 2:1, and 1:1 on a voltage at an input end and then a voltage is output at the two ends of the fourth capacitor Co to implement switching of a plurality of voltage step-down ratios.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.

Abstract: A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.

Abstract: The present disclosure provides a thin film transistor, a display substrate and a display device, and belongs to the field of display technology. The thin film transistor of the present disclosure includes: a base, and a gate, an active layer, a source and a drain located on the base, where the gate includes a first gate and a second gate which are sequentially provided on the base and are electrically connected to each other; the active layer is located between the first gate and the second gate, and orthographic projections of the first gate and the second gate on the base are partially overlapped with an orthographic projection of the active layer on the base, and the orthographic projections of the first gate and the second gate on the base are partially overlapped with each other.

Abstract: Embodiments of the present disclosure provide a display substrate, which has a light-transmissive region. The display substrate includes a substrate, an alignment layer on the substrate, and a convex structure on the alignment layer. The convex structure is on a side of the alignment layer distal to the substrate and does not completely cover the alignment layer. A distance from a surface of the convex structure distal to the substrate to the substrate is greater than a distance from a surface of the alignment layer distal to the substrate to the substrate. The display substrate further comprises a post spacer on a side of the convex structure distal to the alignment layer, the post spacer is located outside the light-transmissive region, and an end surface of the post spacer distal to the convex structure is parallel to a plane where the substrate is located.

Abstract: A method includes forming a first pull-up transistor and a first pass-gate transistor over a substrate at a first level height, the first pull-up and first pass-gate transistors being of a dual port static random access memory (SRAM) cell; forming a first pull-down transistor and a second pass-gate transistor of the dual port SRAM cell over the substrate at a second level height; forming a second pull-down transistor and a third pass-gate transistor of the dual port SRAM cell over the substrate at a third level height; forming a second pull-up transistor and a fourth pass-gate transistor of the dual port SRAM cell over the substrate at a fourth level height.

Abstract: The present invention discloses a micro-sized face-up LED device with a micro-hole array and preparation method thereof. The LED device is prepared based on a GaN-based epitaxial layer and includes a GaN-based epitaxial layer, a current spreading layer, a P electrode, an N electrode and a passivation layer; the GaN-based epitaxial layer including a substrate, an N-type CaN layer, i.e., an N-GaN layer, a multiple quantum well layer (MQW), and a P-type GaN layer, i.e., a P-GaN layer; and the N-GaN layer including an etched exposed N-GaN layer and an etched formed N-GaN layer. The present invention improves luminescence efficiency while ensuring the device modulation bandwidth; and after the micro-hole array is etched by ICP, a sample continues to be etched by using the current spreading layer etching liquid to prevent the leakage caused by the expansion of the current spreading layer in the etching process.

Abstract: A method and a system for automatic machine learning-based prediction of new energy power with cloud-edge collaboration are disclosed. The method includes: obtaining, in response to a power prediction demand for a target new energy station, future numerical weather prediction data of the target new energy station in a future period and historical output power of a historical period corresponding to the future period; selecting, based on missing of the future numerical weather prediction data and a data amount of the historical output power, a target power prediction model corresponding to the target new energy station; and adjusting the target power prediction model according to the target working mode, and predicting, by the adjusted target power prediction model, a target output power of the target new energy station in the future period, based on the future numerical weather prediction data and the historical output power.

Abstract: Provided is a method for shale gas production prediction, including: acquiring real shale gas production data, and determining a target production decline curve model according to the real shale gas production data; setting a time step for production prediction, and obtaining a linear production decline curve by performing production prediction by using the target production decline curve model based on the time step; determining target shale gas production residuals according to the linear production decline curve and the real shale gas production data, inputting the target shale gas production residuals to a long short-term memory, and obtaining a residual prediction result by performing production prediction according to the long short-term memory and the time step; and determining a target production prediction result of shale gas well to be subjected to production prediction based on the linear production decline curve and the residual prediction result.

Abstract: Example power converters and detection methods are described. One example power converter includes a control device, a plurality of wiring terminals, a power conversion circuit, and a plurality of temperature detection devices. The control device is configured to: when an absolute value of a difference between a temperature value of one wiring terminal in the plurality of wiring terminals and a first reference temperature value is greater than or equal to a first temperature difference threshold, output a signal indicating that an abnormality occurs in the plurality of wiring terminals. In this application, a relative change of a temperature of one wiring terminal relative to another wiring terminal can be directly determined based on temperature values of the plurality of wiring terminals, thereby quickly determining, based on a magnitude of the relative change, whether there is an abnormal temperature rise caused by loose connections in the plurality of wiring terminals.

Abstract: A low-cost and high-strength Bi-based superconducting wire/tape and a preparation method thereof, the preparation method includes: 1. subjecting a first Bi-based superconducting wire/tape to electrochemical silver reduction to remove a Ag alloy layer to obtain a second Bi-based superconducting wire/tape; and 2. subjecting the second Bi-based superconducting wire/tape to surface enhancement, such that a Cu layer is formed to obtain the low-cost and high-strength Bi-based superconducting wire/tape. An electrochemical silver reduction technology combines with an electrochemical additive method to remove a Ag alloy layer on a surface of a Bi-based superconducting wire/tape and coat a high-strength Cu layer, such that a low-cost and high-strength Bi-based superconducting wire/tape can be prepared, which reduces a preparation cost and improves a strength of a Bi-based superconducting wire/tape to meet the application requirements of large super-strong magnets.

Abstract: The present disclosure provides a chemical mechanical polishing device including a retaining ring and a wafer carrier and a polishing method. The retaining ring is configured on a polishing pad and includes an inner sidewall defining an opening and an outer sidewall opposite to the inner sidewall. The wafer carrier is configured on the polishing pad and is capable of placing a wafer disposed thereon into the opening and facing the polishing pad. The retaining ring has a notch at the corner adjacent to the wafer and the polishing pad.

Abstract: A semiconductor process for solving contact piping defect is provided in the present invention, including forming gates on a substrate, forming SiN spacers on sidewalls of the gates and the substrate is exposed from the SiN spacers between adjacent gates, performing an epitaxy process to form Si-based sacrificial layers on the gates and the exposed doped areas, and performing a first etchback process using phosphoric acid to pull back the SiN spacers, and the first etchback process removes the Si-based sacrificial layers.

Abstract: The present disclosure provides a chemical mechanical polishing device including a retaining ring and a wafer carrier and a polishing method. The retaining ring is configured on a polishing pad and includes an inner sidewall defining an opening and an outer sidewall opposite to the inner sidewall. The wafer carrier is configured on the polishing pad and is capable of placing a wafer disposed thereon into the opening and facing the polishing pad. The retaining ring has a notch at the corner adjacent to the wafer and the polishing pad.

Abstract: An aerosol generating device includes an aerosol generator and a plug. The aerosol generator includes a container and an atomizing module arranged in the container. The container has a liquid chamber, an aerosol chamber, and an insertion slot defining an insertion direction. The liquid chamber and the aerosol chamber are respectively arranged at two opposite sides of the atomizing module, and are in spatial communication with each other through the atomizing module. The atomizing module includes two electrode regions having the same polarity and being electrically connected to each other. The plug is detachably inserted into the insertion slot of the container along the insertion direction, and a conductive terminal of the plug contacts the two electrode regions.