Patents by Inventor Kai-Yi Wang

Kai-Yi Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12211212
    Abstract: An image segmentation method includes the following steps: obtaining a target image; inputting the target image into a machine learning model to obtain an image segmentation parameter value corresponding to the target image; executing an image segmentation algorithm on the target image according to the image segmentation parameter value to obtain an image segmentation result, wherein the image segmentation result is segmenting the target image into object regions; and displaying the image segmentation result. In addition, an electronic device and storage medium using the method are also provided.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: January 28, 2025
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Yi-Shan Tsai, Cheng-Shih Lai, Chao-Yun Chen, Meng-Jhen Wu, Yun-Chiao Wu, Hsin-Yi Feng, Po-Tsun Kuo, Kai-Yi Wang, Wei-Cheng Su
  • Patent number: 12190506
    Abstract: An interactive image marking method is introduced. The interactive image marking method includes the following steps, displaying a target image and at least one marked region in the target image; receiving an interactive signal, where the interactive signal corresponds to a first pixel of the target image; calculating a correlation between the first pixel and pixels of the target image, and determining a correlation range in the target image according to the correlation; editing the marked region according to the correlate range; and displaying the edited marked region. In addition, an electronic device and a recording medium using the method are also introduced.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: January 7, 2025
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Yi-Shan Tsai, Cheng-Shih Lai, Chao-Yun Chen, Meng-Jhen Wu, Yun-Chiao Wu, Hsin-Yi Feng, Po-Tsun Kuo, Kai-Yi Wang, Wei-Cheng Su
  • Publication number: 20230013609
    Abstract: An interactive image marking method is introduced. The interactive image marking method includes the following steps, displaying a target image and at least one marked region in the target image; receiving an interactive signal, where the interactive signal corresponds to a first pixel of the target image; calculating a correlation between the first pixel and pixels of the target image, and determining a correlation range in the target image according to the correlation; editing the marked region according to the correlate range; and displaying the edited marked region. In addition, an electronic device and a recording medium using the method are also introduced.
    Type: Application
    Filed: December 23, 2021
    Publication date: January 19, 2023
    Inventors: YI-SHAN TSAI, CHENG-SHIH LAI, CHAO-YUN CHEN, MENG-JHEN WU, YUN-CHIAO WU, HSIN-YI FENG, PO-TSUN KUO, KAI-YI WANG, WEI-CHENG SU
  • Publication number: 20230021110
    Abstract: An image segmentation method includes the following steps: obtaining a target image; inputting the target image into a machine learning model to obtain an image segmentation parameter value corresponding to the target image; executing an image segmentation algorithm on the target image according to the image segmentation parameter value to obtain an image segmentation result, wherein the image segmentation result is segmenting the target image into object regions; and displaying the image segmentation result. In addition, an electronic device and storage medium using the method are also provided.
    Type: Application
    Filed: December 23, 2021
    Publication date: January 19, 2023
    Inventors: YI-SHAN TSAI, CHENG-SHIH LAI, CHAO-YUN CHEN, MENG-JHEN WU, YUN-CHIAO WU, HSIN-YI FENG, PO-TSUN KUO, KAI-YI WANG, WEI-CHENG SU
  • Publication number: 20160020166
    Abstract: A trace structure of fine-pitch pattern includes a connection portion, a first conductive wire portion and a second conductive wire portion, the first conductive wire portion comprises a first section and a second section connected to the first section, the first section connects to the connection portion, the second conductive wire portion comprises a third section and a fourth section connected to the third section, the third section connects to the connection portion, wherein an etching space closed on three sides is formed by the connection portion, the third section and the first section, a first spacing is defined between the third section and the first section, a second spacing is defined between the fourth section and the second section, wherein the first spacing is larger than the second spacing so as to make an metal layer within the etching space completely removed to avoid metal layer residues.
    Type: Application
    Filed: October 16, 2014
    Publication date: January 21, 2016
    Inventors: Yung-Wei Hsieh, Cheng-Hung Shih, Kai-Yi Wang, Heh-Chang Huang, Po-Hao Chen
  • Publication number: 20140367856
    Abstract: A semiconductor manufacturing process includes the following steps of providing a silicon substrate having at least one connection pad and a protection layer, forming a first seed layer having at least one first section and at least one second section, forming a first photoresist layer, forming a first buffer layer having a coupling portion and a cladding portion, removing the first photoresist layer, removing the second section of the first seed layer to form a first under bump metallurgy layer, forming a support layer on the protection layer and the first buffer layer, the first under bump metallurgy layer has a first ring wall, the first buffer layer has a second ring wall, wherein the first ring wall, the second ring wall and the cladding portion are cladded by the support layer, and forming a connection portion and covering the coupling portion with the connection portion.
    Type: Application
    Filed: September 2, 2014
    Publication date: December 18, 2014
    Inventors: Cheng-Hung Shih, Yung-Wei Hsieh, Kai-Yi Wang
  • Patent number: 8877629
    Abstract: A semiconductor manufacturing process includes the following steps of providing a silicon substrate having at least one connection pad and a protection layer, forming a first seed layer having at least one first section and at least one second section, forming a first photoresist layer, forming a first buffer layer having a coupling portion and a cladding portion, removing the first photoresist layer, removing the second section of the first seed layer to form a first under bump metallurgy layer, forming a support layer on the protection layer and the first buffer layer, the first under bump metallurgy layer has a first ring wall, the first buffer layer has a second ring wall, wherein the first ring wall, the second ring wall and the cladding portion are cladded by the support layer, and forming a connection portion and covering the coupling portion with the connection portion.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: November 4, 2014
    Assignee: Chipbond Technology Corporation
    Inventors: Cheng-Hung Shih, Yung-Wei Hsieh, Kai-Yi Wang
  • Publication number: 20140159234
    Abstract: A semiconductor manufacturing process includes the following steps of providing a silicon substrate having at least one connection pad and a protection layer, forming a first seed layer having at least one first section and at least one second section, forming a first photoresist layer, forming a first buffer layer having a coupling portion and a cladding portion, removing the first photoresist layer, removing the second section of the first seed layer to form a first under bump metallurgy layer, forming a support layer on the protection layer and the first buffer layer, the first under bump metallurgy layer has a first ring wall, the first buffer layer has a second ring wall, wherein the first ring wall, the second ring wall and the cladding portion are cladded by the support layer, and forming a connection portion and covering the coupling portion with the connection portion.
    Type: Application
    Filed: January 17, 2013
    Publication date: June 12, 2014
    Applicant: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Cheng-Hung Shih, Yung-Wei Hsieh, Kai-Yi Wang
  • Publication number: 20080199394
    Abstract: The invention, firstly, SnCl4 and SbCl3 are collected as raw materials and all dissolved into water and hydrochloric acid with precipitation. Secondly, NaOH or NH40H can be used for adjusting the pH value. Then, aging, water-washing, filtering and drying process are all carried out. The additive also can be put into and sintering process is applied. Furthermore, washing and drying process are used for obtaining the crystalline nano-level acicular ATO composition powder.
    Type: Application
    Filed: February 15, 2007
    Publication date: August 21, 2008
    Applicant: Chang Gung University
    Inventors: Hsin-Chun Lu, Mei-Ching Chiang, Kai-Yi Wang, Yu-Hsiang Lin