Abstract: A mechanism for processing video data is disclosed. One or more extended taps are determined for use in an adaptive loop filter (ALF). A conversion is performed between a visual media data and a bitstream based on the extended tap in the ALF. The extended tap may receive input data from different pictures than the current picture and/or from outside the spatial domain.

Abstract: A mechanism for processing video data is disclosed. A filter is applied to a video unit. The filter employs an extended tap for a first sample in the video unit and a spatial tap for a second sample in the video unit. A conversion is performed between a visual media data and a bitstream based on the video unit.

Abstract: Examples of user equipments (UEs) are described. A UE includes receiving circuitry configured to receive first information to configure one or more channel state information-reference signals (CSI-RS) for tracking and second information to configure time domain correlation related information. The UE also includes transmitting circuitry configured to transmit a channel state information (CSI) report including the time domain correlation related information. A first parameter trs-Info is included in the first information. A second parameter reportQuantity is not set to ‘none’. The time domain correlation related information is measured by the one or more CSI-RS for tracking.

Abstract: Provided is a multilayer unsupported glove comprising: (A) an outer, first layer of polymer content comprising about 55 wt % or more chloroprene, from 0 wt % to up to about 45 wt % nitrile comprising carboxylated nitrile, and no more than about 5 wt % of another polymer; and (B) laminated to the outer layer, second layer of polymer content that is substantially nitrile 90 wt % or more, wherein the glove is about 0.16 mm or less in thickness, has a tensile strength unaged of greater than about 17 mPa pursuant to ASTM D412:2016 (E 2021) or a tensile strength aged of greater than about 23 MPa, and is accelerator free.

Abstract: A test socket for 224 Gbps ultra-high-speed coaxial testing includes a test socket body made of metal and a test socket cover plate. The test socket body is provided with mounting holes, within which are set first polymer positioning parts that match the holes. The first polymer positioning part is provided with first and second insertion holes, into which test probes are respectively inserted. The test socket cover plate is fixedly provided with a second polymer positioning part, which has a first positioning hole that matches the first polymer positioning part, and a second positioning hole that is connected to the first positioning hole and matches the end of the test probe. The height of the first polymer positioning part is less than the length of the test probe, achieving a large dynamic bandwidth and high isolation for the coaxial test socket for ultra-high-speed testing frequencies.

Abstract: A polarizer and a liquid crystal display device are disclosed. The polarizer includes a first protection film, a polarization layer, a second protection film, a chroma viewing angle enhancement layer, and a surface protection film laminated. Material of the chroma viewing angle enhancement layer includes a resin composite. The resin composite includes a light diffusion agent. The light diffusion agent is aligned in the chroma viewing angle enhancement layer, an acute angle is defined between a long axis direction of light diffusion agent and a bottom surface of the chroma viewing angle enhancement layer, and the acute angle is greater than 0° and is less than or equal to 40°.

Abstract: The power distribution component is configured to connect to a power distribution box in a pluggable manner. A main body is provided with a first power terminal, a signal terminal, and a second power terminal that are arranged along a first direction. The first power terminal is configured to electrically connect to a first power busbar of the power distribution box, the signal terminal is configured to electrically connect to a signal busbar of the power distribution box, and the second power terminal is configured to electrically connect to a second power busbar of the power distribution box. Polarities of the first power terminal and the second power terminal are opposite. An end, facing away from the main body, of the mistake proofing structure is provided with an abutting surface, configured to abut against the signal busbar when the power distribution component is reversely inserted into the power distribution box.

Abstract: Provided is a multilayer unsupported glove comprising: (A) an outer, first layer of polymer content comprising about 55 wt % or more chloroprene, from 0 wt % to up to about 45 wt % nitrile comprising carboxylated nitrile, and no more than about 5 wt % of another polymer; and (B) laminated to the outer layer, second layer of polymer content that is substantially nitrile 90 wt % or more, wherein the glove is about 0.16 mm or less in thickness, has a tensile strength unaged of greater than about 17 mPa pursuant to ASTM D412:2016 (E 2021) or a tensile strength aged of greater than about 23 MPa, and is accelerator free.

Abstract: The present application relates to a method (I) for preparing a brivaracetam intermediate, comprising the steps of dissolving the compound represented by B-P and 1S,2S-diphenylethylenediamine in a solvent for resolution, crystallizing, filtering, and recrystallizing to obtain the compound represented by B-Q, which is then converted to the brivaracetam intermediate represented by B-R. This method can effectively resolve the compound represented by B-P. The present application also provides a method for preparing brivaracetam using the compound represented by B-R. The method can separate the effective components only through simple steps such as extraction, washing, drying, and concentration without requiring use of chiral chromatography column to separate isomers in the preparation process, and thus the separation process is simple, greatly reducing the production cost of brivaracetam.

Abstract: Provided is a multilayer unsupported glove comprising: (A) an outer, first layer of polymer content comprising about 55 wt % or more chloroprene, from 0 wt % to up to about 45 wt % nitrile comprising carboxylated nitrile, and no more than about 5 wt % of another polymer; and (B) laminated to the outer layer, second layer of polymer content that is substantially nitrile 90 wt % or more, wherein the glove is about 0.16 mm or less in thickness, has a tensile strength unaged of greater than about 17 mPa pursuant to ASTM D412:2016 (E 2021) or a tensile strength aged of greater than about 23 MPa, and is accelerator free.

Abstract: The present invention discloses a SAADC circuit having optimized linearity. A lower-bit capacitor array includes lower-bit capacitors. A higher-bit capacitor array includes unit capacitors. In an initializing mode, a control circuit sorts the unit capacitors according to unit capacitances thereof such that the unit capacitors are configured to be higher-bit capacitors having a linearity parameter within a predetermined range. In an operation mode, the capacitor array receives an analog input signal and a reference voltage to generate an analog output signal, a comparator generates a comparison result according to the analog output signal and the control circuit generates an enabling signal according to the comparison result based on the successive approximation mechanism to selectively enable the higher-bit and the lower-bit capacitors to connect to the reference voltage by using the capacitor enabling circuit and outputs a digital output signal according to the final comparison result.

Abstract: A voltage regulation integrated circuit (IC) includes a first transistor, a feedback circuit, a bias circuit, an amplifier circuit, and a transient coupling circuit. The first transistor is configured to generate an output voltage according to an input voltage and a control voltage. The feedback circuit is configured to generate a feedback voltage according to the output voltage. The output voltage includes an AC component. The bias circuit is configured to generate a first bias voltage. The amplifier circuit is configured to generate the control voltage according to the first bias voltage and the feedback voltage. The transient coupling circuit is configured to generate a coupling voltage according to the AC component and to assist the change of the first bias voltage according to the coupling voltage, so that the output voltage is maintained at a voltage level.

Abstract: Disclosed is a method for preparing a brivaracetam intermediate shown in formula B-R, comprising: reacting a compound shown in formula B-P and a resolving agent to prepare a compound shown in formula B-Q; and converting the compound shown in formula B-Q into the brivaracetam intermediate shown in formula B-R, wherein the resolving agent is a (1S,2S)-(+)-1,2-diaminocyclohexane compound. Also provided is a method for preparing brivaracetam. According to the method, a mixture of two diastereoisomers of (S)-2-3-propylpyrrolidine-1-yl butyric acid can be conveniently and effectively resolved, and the use of a chiral HPLC column is avoided, thereby greatly shortening the process time, simplifying the operation, reducing the process cost, and facilitating industrial production and enviormental protection.

Abstract: The present invention discloses a programmable gain amplifier having mode-switching mechanism. An operational amplifier includes a first input terminal, a second input terminal and an output terminal. The second input terminal is coupled to a ground terminal. The output terminal generates an output signal. A variable resistor and a first switch are coupled in series between a first terminal and a second terminal that coupled to the first input terminal. A first variable capacitor and a second switch are coupled in series between the first terminal and the second terminal. A second variable capacitor and a third switch are coupled in series between the first terminal and the ground terminal. A low-pass resistor and a low-pass capacitor are coupled in parallel between the first input terminal and the output terminal. An input resistor is coupled between a signal input terminal and the first terminal to receive an input signal from the signal input terminal.

Abstract: An electronic package structure and a chip thereof are provided. The electronic package structure includes a supporting element, a chip, an internal bonding wire, and a plurality of external bonding wires. The supporting element has a chip arrangement portion. The chip has a first surface and a second surface opposite to the first surface. The chip is arranged on the chip arrangement portion with the second surface facing toward the supporting element. The chip includes a first common pad and an individual core pad that are disposed on the first surface. The internal bonding wire is connected between the first common pad and the individual core pad. The external bonding wires are connected between the chip and the supporting element, in which a first external bonding wire of the external bonding wires and the internal bonding wire are jointly connected to the first common pad.

Abstract: An analog-to-digital converter includes a switch circuit, a first capacitor array, a second capacitor array and a comparator. A method of operating the analog-to-digital converter includes switching a swap signal to a first level in a first sampling period for the switch circuit to couple the first capacitor array to a first input terminal of the comparator and a first signal source, and couple the second capacitor array to a second input terminal of the comparator and a second signal source, and switching the swap signal to a second level in a second sampling period for the switch circuit to couple the first capacitor array to the second input terminal of the comparator and the second signal source, and couple the second capacitor array to the first input terminal of the comparator and the first signal source.

Abstract: A method of operating an analog-to-digital converter includes in a first conversion period, a comparator generating a first comparison result, a first selection circuit switching a voltage output to a first capacitor of a set of larger capacitor of a first capacitor array, and a second selection circuit switching a voltage output to a second capacitor of a set of larger capacitor of a second capacitor array, and in a second conversion period after the first conversion period, the comparator generating a second comparison result different from the first comparison result, the first selection circuit switching back the voltage output to a first capacitor portion of the first capacitor of the set of larger capacitor of the first capacitor array, and the second selection circuit switching back the voltage output to a first capacitor portion of the second capacitor of the set of larger capacitor of the second capacitor array.

Abstract: Saliency tracking for brushless direct current (BLDC) motors and other permanent magnet synchronous motors (PMSMs) is provided. Embodiments generate an accurate estimate of rotor position for use in field-oriented control (FOC) of BLDC motors. In addition, a robust saliency tracking algorithm provides for the use of BLDC motors in low-speed high-torque applications without the need of external sensors. This enables sensorless application of higher level algorithms as well, such as servo control. In addition, accurate measurement of motor phase inductance and flux linkage can be provided without any additional equipment.

Abstract: An encrypted data storage system and method based on offsite key storage are provided, comprising the system includes a key control center, an offsite key storage system, and a data encryption/decryption storage system. The offsite key storage system includes a first key control device, a key storage device, and a first quantum key distribution device. The data encryption/decryption storage system includes a second key control device, a data encryption/decryption storage device, and a second quantum key distribution device. The first quantum key distribution device is in quantum communication connection with the second quantum key distribution device. The first key control device is communicatively connected with the key storage device and the first quantum key distribution device, respectively.

Abstract: Disclosed is a voltage reference buffer circuit including a first, second, third, and fourth bias generators and a first, second, third, and fourth driving components. The first, second, third, and fourth bias generators generate bias voltages to control the first, second, third, and fourth driving components respectively. The first, second, third, and fourth driving components are coupled in sequence, wherein the first and second driving components are different types of transistors and jointly output a first reference voltage, the third and fourth driving components are different types of transistors and jointly output a second reference voltage, and the group of the first and second driving components is separated from the group of the third and fourth driving components by a resistance load.