Patents by Inventor Kai-Ying Wang

Kai-Ying Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11974228
    Abstract: An apparatus (e.g., an access point (AP) or a non-AP station (STA)) detects a non-primary subband of an operating bandwidth comprising a primary subband and the non-primary subband to be idle. The apparatus controls a transmit power in performing transmission on at least the non-primary subband.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: April 30, 2024
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Kai Ying Lu, Hung-Tao Hsieh, Yen-Shuo Lu, Chao-Chun Wang, James Chih-Shi Yee, Yongho Seok
  • Patent number: 11955579
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of light-emitting elements on a first substrate and forming a first pattern array on a second substrate, wherein the first pattern array includes an adhesive layer. The method also includes transferring the plurality of light-emitting elements from the first substrate to the second substrate and forming the first pattern array on a third substrate. The method includes transferring the plurality of light-emitting elements from the second substrate to the third substrate, and reducing an adhesion force of a portion of the adhesive layer. The method also includes forming a second pattern array on a fourth substrate, and transferring the plurality of light-emitting elements from the third substrate to the fourth substrate. The pitch between the plurality of light-emitting elements on the first substrate is different than the pitch of the first pattern array.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: April 9, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Kai Cheng, Tsau-Hua Hsieh, Fang-Ying Lin, Tung-Kai Liu, Hui-Chieh Wang, Chun-Hsien Lin, Jui-Feng Ko
  • Patent number: 11949040
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of diodes on a first substrate and forming a first pattern array on a second substrate. The method also includes transferring the plurality of diodes from the first substrate to the second substrate. The method further includes forming the first pattern array on a third substrate. In addition, the method includes transferring the plurality of diodes from the second substrate to the third substrate. The method also includes forming a second pattern array on a fourth substrate. The method further includes transferring the plurality of diodes from the third substrate to the fourth substrate. The pitch between the plurality of diodes on the first substrate is different from the pitch of the first pattern array.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: April 2, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Kai Cheng, Tsau-Hua Hsieh, Fang-Ying Lin, Tung-Kai Liu, Hui-Chieh Wang, Chun-Hsien Lin, Jui-Feng Ko
  • Publication number: 20240073773
    Abstract: Various techniques and schemes pertaining to extremely-high throughput (EHT) multi-link maximum channel switching in wireless communications are described. A station (STA) multi-link device (MLD) receives an indication from a reporting access point (AP) affiliated with an AP MLD on one link of multiple links. The STA MLD determines a channel switching time when a reported AP switches from operating in a current channel of the reported AP to operating in a new channel on one other link of the multiple links based on the indication.
    Type: Application
    Filed: August 16, 2023
    Publication date: February 29, 2024
    Inventors: Yongho Seok, Chao-Chun Wang, Kai Ying Lu, James Chih-Shi Yee, Gabor Bajko
  • Patent number: 8421179
    Abstract: A Schottky diode with high antistatic capability has an N? type doped drift layer formed on an N+ type doped layer. The N? type doped drift layer has a surface formed with a protection ring. Inside the protection ring is a P-type doped area. The N? type doped drift layer surface is further formed with an oxide layer and a metal layer. The contact region between the metal layer and the N? type doped drift layer and the P-type doped area forms a Schottky contact. The P-type doped area has a low-concentration lower layer and a high-concentration upper layer, so that the surface ion concentration is high in the P-type doped area. The Schottky diode thus has such advantages of lowered forward voltage drop and high antistatic capability.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: April 16, 2013
    Assignee: Pynmax Technology Co., Ltd.
    Inventors: Chiun-Yen Tung, Kun-Hsien Chen, Kai-Ying Wang, Wen-Li Tsai
  • Publication number: 20120205771
    Abstract: A Schottky diode with a low forward voltage drop has an N? type doped drift layer formed on an N+ type doped layer. The N? type doped drift layer has a first surface with a protection ring inside which is a P-type doped area. The N? type doped drift layer surface is further formed with an oxide layer and a metal layer. The contact region between the metal layer and the N? type doped drift layer and the P-type doped area forms a Schottky barrier. The height of the Schottky barrier is lower than the surface of the N? type doped drift layer, thereby reducing the thickness of the N? type doped drift layer under the Schottky barrier. This configuration reduces the forward voltage drop of the Schottky barrier.
    Type: Application
    Filed: July 20, 2011
    Publication date: August 16, 2012
    Applicant: PYNMAX TECHNOLOGY CO., LTD.
    Inventors: Chiun-Yen TUNG, Kai-Ying WANG, Chia-Ling LU, Kuo-Hsien WU, Kun-Hsien CHEN
  • Publication number: 20120205770
    Abstract: A Schottky diode with high antistatic capability has an N? type doped drift layer formed on an N+ type doped layer. The N? type doped drift layer has a surface formed with a protection ring. Inside the protection ring is a P-type doped area. The N? type doped drift layer surface is further formed with an oxide layer and a metal layer. The contact region between the metal layer and the N? type doped drift layer and the P-type doped area forms a Schottky contact. The P-type doped area has a low-concentration lower layer and a high-concentration upper layer, so that the surface ion concentration is high in the P-type doped area. The Schottky diode thus has such advantages of lowered forward voltage drop and high antistatic capability.
    Type: Application
    Filed: July 20, 2011
    Publication date: August 16, 2012
    Applicant: PYNMAX TECHNOLOGY CO., LTD.
    Inventors: Chiun-Yen TUNG, Kun-Hsien CHEN, Kai-Ying WANG, Wen-Li TSAI
  • Publication number: 20110163408
    Abstract: A Schottky diode structure with low reverse leakage current and low forward voltage drop has a first conductive material semiconductor substrate combined with a metal layer. An oxide layer is formed around the edge of the combined conductive material semiconductor substrate and the metal layer. A plurality of dot-shaped or line-shaped second conductive material regions are formed on the surface of the first conductive material semiconductor substrate connecting to the metal layer. The second conductive material regions form depletion regions in the first conductive material semiconductor substrate. The depletion regions can reduce the leakage current area of the Schottky diode, thereby reducing the reverse leakage current and the forward voltage drop. When the first conductive material is a P-type semiconductor, the second conductive material is an N-type semiconductor. When the first conductive material is an N-type semiconductor, the second conductive material is a P-type semiconductor.
    Type: Application
    Filed: January 6, 2010
    Publication date: July 7, 2011
    Inventors: Chiun-Yen Tung, Kun-Hsien Chen, Kai-Ying Wang, Hung Ta Weng, Yi-Chen Shen