Patents by Inventor Kai-Yu Cheng

Kai-Yu Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240024764
    Abstract: An expansion device includes a device body, which includes two carrying structures and a first elastic component, and a clamping structure. The two carrying structures are slidably disposed on each other, each carrying structure has a carrying portion and a clamping portion, and the carrying portion carries an electronic device. The first elastic component is connected to the two carrying structures and causes the two carrying structures to slide from a first state to a second state with variation of an elastic potential energy thereof, and the two clamping portions clamp the electronic device between the first state and the second state. The clamping structure includes a clamping component and a second elastic component. The clamping component is movably disposed on the carrying structure. The second elastic component causes the clamping component to move form a first position to a second position with variation of an elastic potential energy thereof.
    Type: Application
    Filed: November 10, 2022
    Publication date: January 25, 2024
    Applicant: Chicony Electronics Co., Ltd.
    Inventor: Kai-Yu Cheng
  • Patent number: 11508849
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Cheng Chang, Kai-Yu Cheng, Chih-Han Lin, Sin-Yi Yang, Horng-Huei Tseng
  • Publication number: 20200328308
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Inventors: Che-Cheng Chang, Kai-Yu Cheng, Chih-Han Lin, Sin-Yi Yang, Horng-Huei Tseng
  • Patent number: 10756192
    Abstract: A semiconductor device having a composite barrier structure over a transistor and a method for manufacturing the same is disclosed. The method includes a series of steps including: forming a transistor having source/drain regions within a fin structure and adjacent to a gate structure across over the fin structure; forming first source/drain contacts right above and electrically connected to the source/drain regions; depositing a composite barrier structure over the transistor and the first source/drain contacts; and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method further includes depositing a second etch-stop layer before depositing the composite barrier structure and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method also includes forming contacts over and electrically connected to the second source/drain contacts.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventor: Kai-Yu Cheng
  • Patent number: 10700208
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Kai-Yu Cheng, Chih-Han Lin, Sin-Yi Yang, Horng-Huei Tseng
  • Patent number: 10409482
    Abstract: The present invention provides a touch sensitive processing method for switch an electronic system into a normal operation mode upon receiving a touch gesture in a power saving mode. The electronic system includes a host and a power supply module. The host is configured to execute an operating system to control the electronic system in the normal operation mode. The power supply module is configured to supply power to the host in the normal operation mode and to cut power supply to the host in the power saving mode. The touch sensitive processing method includes: detecting multiple touch events via multiple touch sensitive electrodes of a touch panel; determining whether a power-on command is formed by these touch events; and sending a power-on notification to the power supply module for supplying power to the host and switching to the normal operation mode when the power-on command is formed by these touch events.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 10, 2019
    Assignee: EGALAX_EMPIA TECHNOLOGY INC.
    Inventor: Kai-Yu Cheng
  • Publication number: 20190148553
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.
    Type: Application
    Filed: December 18, 2018
    Publication date: May 16, 2019
    Inventors: Che-Cheng Chang, Kai-Yu Cheng, Chih-Han Lin, Sin-Yi Yang, Horng-Huei Tseng
  • Patent number: 10269705
    Abstract: A semiconductor structure includes a first dielectric layer, a first conductive via, a partial landing pad, a second dielectric layer, and a second conductive via. The first conductive via is disposed in the first dielectric layer. The partial landing pad is disposed on the first conductive via and the first dielectric layer, in which the partial landing pad has a top surface and a bottom surface, and the top surface of the partial landing pad has a width greater than or substantially equal to that of the bottom surface of the partial landing pad. The second dielectric layer is disposed on the partial landing pad. The second conductive via is disposed in the second dielectric layer and electrically connected to the partial landing pad.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Yu Cheng, Shih-Kang Tien, Ching-Kun Huang
  • Publication number: 20190103469
    Abstract: A semiconductor device having a composite barrier structure over a transistor and a method for manufacturing the same is disclosed. The method includes a series of steps including: forming a transistor having source/drain regions within a fin structure and adjacent to a gate structure across over the fin structure; forming first source/drain contacts right above and electrically connected to the source/drain regions; depositing a composite barrier structure over the transistor and the first source/drain contacts; and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method further includes depositing a second etch-stop layer before depositing the composite barrier structure and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method also includes forming contacts over and electrically connected to the second source/drain contacts.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 4, 2019
    Inventor: Kai-Yu Cheng
  • Patent number: 10164035
    Abstract: A semiconductor device having a composite barrier structure over a transistor and a method for manufacturing the same is disclosed. The method includes a series of steps including: forming a transistor having source/drain regions within a fin structure and adjacent to a gate structure across over the fin structure; forming first source/drain contacts right above and electrically connected to the source/drain regions; depositing a composite barrier structure over the transistor and the first source/drain contacts; and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method further includes depositing a second etch-stop layer before depositing the composite barrier structure and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method also includes forming contacts over and electrically connected to the second source/drain contacts.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventor: Kai-Yu Cheng
  • Patent number: 10164111
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Kai-Yu Cheng, Chih-Han Lin, Sin-Yi Yang, Horng-Huei Tseng
  • Publication number: 20180247890
    Abstract: A semiconductor structure includes a first dielectric layer, a first conductive via, a partial landing pad, a second dielectric layer, and a second conductive via. The first conductive via is disposed in the first dielectric layer. The partial landing pad is disposed on the first conductive via and the first dielectric layer, in which the partial landing pad has a top surface and a bottom surface, and the top surface of the partial landing pad has a width greater than or substantially equal to that of the bottom surface of the partial landing pad. The second dielectric layer is disposed on the partial landing pad. The second conductive via is disposed in the second dielectric layer and electrically connected to the partial landing pad.
    Type: Application
    Filed: April 27, 2018
    Publication date: August 30, 2018
    Inventors: Kai-Yu Cheng, Shih-Kang Tien, Ching-Kun Huang
  • Patent number: 9984967
    Abstract: A semiconductor structure includes a first dielectric layer, a first conductive via, a partial landing pad, a second dielectric layer, and a second conductive via. The first conductive via is disposed in the first dielectric layer. The partial landing pad is disposed on the first conductive via and the first dielectric layer, in which the partial landing pad has a top surface and a bottom surface, and the top surface of the partial landing pad has a width greater than or substantially equal to that of the bottom surface of the partial landing pad. The second dielectric layer is disposed on the partial landing pad. The second conductive via is disposed in the second dielectric layer and electrically connected to the partial landing pad.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Yu Cheng, Shih-Kang Tien, Ching-Kun Huang
  • Publication number: 20180107373
    Abstract: The present invention provides a touch sensitive processing method for switch an electronic system into a normal operation mode upon receiving a touch gesture in a power saving mode. The electronic system includes a host and a power supply module. The host is configured to execute an operating system to control the electronic system in the normal operation mode. The power supply module is configured to supply power to the host in the normal operation mode and to cut power supply to the host in the power saving mode. The touch sensitive processing method includes: detecting multiple touch events via multiple touch sensitive electrodes of a touch panel; determining whether a power-on command is formed by these touch events; and sending a power-on notification to the power supply module for supplying power to the host and switching to the normal operation mode when the power-on command is formed by these touch events.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 19, 2018
    Inventor: KAI-YU CHENG
  • Publication number: 20180047819
    Abstract: A semiconductor device having a composite barrier structure over a transistor and a method for manufacturing the same is disclosed. The method includes a series of steps including: forming a transistor having source/drain regions within a fin structure and adjacent to a gate structure across over the fin structure; forming first source/drain contacts right above and electrically connected to the source/drain regions; depositing a composite barrier structure over the transistor and the first source/drain contacts; and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method further includes depositing a second etch-stop layer before depositing the composite barrier structure and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method also includes forming contacts over and electrically connected to the second source/drain contacts.
    Type: Application
    Filed: October 23, 2017
    Publication date: February 15, 2018
    Inventor: Kai-Yu Cheng
  • Publication number: 20180040733
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.
    Type: Application
    Filed: December 29, 2016
    Publication date: February 8, 2018
    Inventors: Che-Cheng Chang, Kai-Yu Cheng, Chih-Han Lin, Sin-Yi Yang, Horng-Huei Tseng
  • Patent number: 9799741
    Abstract: A semiconductor device having a composite barrier structure over a transistor and a method for manufacturing the same is disclosed. The method includes a series of steps including: forming a transistor having source/drain regions within a fin structure and adjacent to a gate structure across over the fin structure; forming first source/drain contacts right above and electrically connected to the source/drain regions; depositing a composite barrier structure over the transistor and the first source/drain contacts; and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method further includes depositing a second etch-stop layer before depositing the composite barrier structure and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method also includes forming contacts over and electrically connected to the second source/drain contacts.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: October 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Kai-Yu Cheng
  • Publication number: 20170179021
    Abstract: A semiconductor structure includes a first dielectric layer, a first conductive via, a partial landing pad, a second dielectric layer, and a second conductive via. The first conductive via is disposed in the first dielectric layer. The partial landing pad is disposed on the first conductive via and the first dielectric layer, in which the partial landing pad has a top surface and a bottom surface, and the top surface of the partial landing pad has a width greater than or substantially equal to that of the bottom surface of the partial landing pad. The second dielectric layer is disposed on the partial landing pad. The second conductive via is disposed in the second dielectric layer and electrically connected to the partial landing pad.
    Type: Application
    Filed: March 9, 2016
    Publication date: June 22, 2017
    Inventors: Kai-Yu CHENG, Shih-Kang TIEN, Ching-Kun HUANG
  • Publication number: 20170179245
    Abstract: A semiconductor device having a composite barrier structure over a transistor and a method for manufacturing the same is disclosed. The method includes a series of steps including: forming a transistor having source/drain regions within a fin structure and adjacent to a gate structure across over the fin structure; forming first source/drain contacts right above and electrically connected to the source/drain regions; depositing a composite barrier structure over the transistor and the first source/drain contacts; and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method further includes depositing a second etch-stop layer before depositing the composite barrier structure and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method also includes forming contacts over and electrically connected to the second source/drain contacts.
    Type: Application
    Filed: February 25, 2016
    Publication date: June 22, 2017
    Inventor: Kai-Yu CHENG
  • Patent number: 9098848
    Abstract: The present invention is a safety covering design for financial transaction device, simply constructing specific solid connection between boards by the pressure formed after assembly. The pressure is formed with assembly and constructing connection of units, so illegally penetration can be easily detected, because the pressure is released by disassembly as well as the connection between boards is removed. Thus, the financial transaction device of the present invention is not easy being penetrated without alarm.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: August 4, 2015
    Assignee: CASTLES TECHNOLOGY CO., LTD.
    Inventors: Hung-Chun Lin, Kai-Yu Cheng